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Disable GPMC bus related pin on OMAP35xx

Cyril HAENEL
Prodigy 60 points

Hello, I designed a mother board based on a OMAP35xx processor, and we have the possibility to connect daugher board on this mother board.

One of our daugher board is an ethernet board, and for very low consumption during power saving mode (when the ethernet is not used), we can completely power down the supply of the ethernet board.

But before to do that, I want to disable all GPMC related pin of the processor to not have any logic 1 on the ethernet chip (which is powered down).

With multiplexing register, I can successfully set gpmc_d8-->gpmc_d15, gpmc_a1->gpmc_a7 and gpmc_ncs5 in input with pull down, which is great.

But I am not able to disable gpmc_d0-->gpmc_d7, gpmc_noe, gpmc_nwe :(

Do you think there is another way to disable them ?

Regards

Cyril

  • 0
    TI__Guru 65405 points

    Hi Cyril,

    I would like to ask you where you set the pin mux configuration - in the uboot or in the kernel. If you make the pin mux settings in the uboot they could be overwritten in the kernel and the pull down setting to be removed. Therefore I suggest you to compare the pin mux configuration of both groups of pins in the kernel and check whether check their pull down status.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 60 points

    I change the MUX config directly in linux, with devmem2 tool.

    But in the hardware datasheet (Table 7-77), the bits to switch the pin as GPIO don't exist, for example for d0-d7 :

    REGISTER NAME Pad Name Physical WakeUpx OffMode Input Reserved PU/PD MuxMode
    CONTROL_PADCONF_SDRC_CLK[31:16] sdrc_dqs0 0x4800 2070 -- ----- 0b1 0b000 0b00 ---
    CONTROL_PADCONF_SDRC_DQS1[15:0] sdrc_dqs1 0x4800 2074 -- ----- 0b1 0b000 0b00 ---
    CONTROL_PADCONF_SDRC_DQS1[31:16] sdrc_dqs2 0x4800 2074 -- ----- 0b1 0b000 0b00 ---
    CONTROL_PADCONF_SDRC_DQS3[15:0] sdrc_dqs3 0x4800 2078 -- ----- 0b1 0b000 0b00 ---
    CONTROL_PADCONF_SDRC_DQS3[31:16] gpmc_a1 0x4800 2078 0b00 0b00000 0b1 0b000 0b01 0b111
    CONTROL_PADCONF_GPMC_A2[15:0] gpmc_a2 0x4800 207C 0b00 0b00000 0b1 0b000 0b01 0b111
    CONTROL_PADCONF_GPMC_A2[31:16] gpmc_a3 0x4800 207C 0b00 0b00000 0b1 0b000 0b01 0b111
    CONTROL_PADCONF_GPMC_A4[15:0] gpmc_a4 0x4800 2080 0b00 0b00000 0b1 0b000 0b01 0b111
    CONTROL_PADCONF_GPMC_A4[31:16] gpmc_a5 0x4800 2080 0b00 0b00000 0b1 0b000 0b01 0b111
    CONTROL_PADCONF_GPMC_A6[15:0] gpmc_a6 0x4800 2084 0b00 0b00000 0b1 0b000 0b11 0b111
    CONTROL_PADCONF_GPMC_A6[31:16] gpmc_a7 0x4800 2084 0b00 0b00000 0b1 0b000 0b11 0b111
    CONTROL_PADCONF_GPMC_A8[15:0] gpmc_a8 0x4800 2088 0b00 0b00000 0b1 0b000 0b11 0b111
    CONTROL_PADCONF_GPMC_A8[31:16] gpmc_a9 0x4800 2088 0b00 0b00000 0b1 0b000 0b11 0b111
    CONTROL_PADCONF_GPMC_A10[15:0] gpmc_a10 0x4800 208C 0b00 0b00000 0b1 0b000 0b11 0b111
    CONTROL_PADCONF_GPMC_A10[31:16] gpmc_d0 0x4800 208C -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D1[15:0] gpmc_d1 0x4800 2090 -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D1[31:16] gpmc_d2 0x4800 2090 -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D3[15:0] gpmc_d3 0x4800 2094 -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D3[31:16] gpmc_d4 0x4800 2094 -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D5[15:0] gpmc_d5 0x4800 2098 -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D5[31:16] gpmc_d6 0x4800 2098 -- 0b00000 0b1 0b000 0b11 ---
    CONTROL_PADCONF_GPMC_D7[15:0] gpmc_d7 0x4800 209C -- 0b00000 0b1 0b000 0b11 ---

    CONTROL_PADCONF_GPMC_D7[31:16] gpmc_d8 0x4800 209C 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D9[15:0] gpmc_d9 0x4800 20A0 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D9[31:16] gpmc_d10 0x4800 20A0 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D11[15:0] gpmc_d11 0x4800 20A4 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D11[31:16] gpmc_d12 0x4800 20A4 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D13[15:0] gpmc_d13 0x4800 20A8 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D13[31:16] gpmc_d14 0x4800 20A8 0b00 0b00000 0b1 0b000 0b11 0b000
    CONTROL_PADCONF_GPMC_D15[15:0] gpmc_d15 0x4800 20AC 0b00 0b00000 0b1 0b000 0b11 0b000

    Thus for some GPMC bits I can easily disable the pin (input mode + pull down), with 0x109 instead 0x118 for example for gpmc_d8 --> gpmc_d15.

    But for gpmc_d0 --> gpmc_d7, gpmc_noe, gpmc_nwe, gpmc_ncs5, unfortunally the MuxMode bits are not available and I can't disable the pin.

    I there another way or a trick to be able to disable these pin or set them to logical 0 level ?

    Regards