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Dm816x GPIO Debouncing

Sachin G Anvekar1
Prodigy 110 points
Other Parts Discussed in Thread: CCSTUDIO

Hi,

We have a query regarding debouncing feature of GPIO pins. We have enabled the interrupts (rising and falling edge) for the required GPIO pin ,but because of lot of bouncing we are getting too many interrupts. In order to mitigate that we did the following settings:

  1. Set the GPIO_DEBOUNCINGTIME register with required debouncing time.
  2. Set the GPIO_DEBOUNCENABLE register for the required GPIO pin.

But now we are not able to see any interrupts at all. When we disable the debounce feature of GPIO pin, interrupts are observed. Also, we have set the CM_SYSCLK18_CLKSEL register to 1 since we don’t have an external 32.768KHz  crystal clocked in to the DM816x chip.

Please let us know the reason for not getting any interrupts when debouncing feature is enabled.

Regards,
Sachin

  • 0
    TI__Guru**** 170625 points

    Sachin,

    Are you using DM816x EZSDK 5.05.02.00?

    Are you using DM816x EVM or custom board?

    See if the below wiki pages will be in help:

    http://processors.wiki.ti.com/index.php/Configuring_GPIO_Interrupts

    http://processors.wiki.ti.com/index.php/Avoiding_Double_Interrupts_with_the_GPIO_Peripheral

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 110 points

    Hi Pavel,

    We are aware of configuring GPIO interrupts. Those wiki pages are for configuring GPIO interrupts. As mentioned in my post, when we disable the GPIO debounce feature we are getting lot of interrupts due to bouncing (ideally we should get only two interrupts for rising and falling edge respectively) but when we enable GPIO debouncing feature there are no interrupts at all. Can you please look into it.

    We are using DM816x custom board.

    Regards,

    Sachin

  • 0 in reply to Sachin G Anvekar1
    TI__Guru**** 170625 points

    Sachin,

    Sachin G Anvekar1 said:
    We are using DM816x custom board.

    Can you try reproduce this issue on the DM816x EVM?

    Are you using DM816x EZSDK 5.05.02.00? Or CCStudio/JTAG project? Or else?

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    TI__Guru*** 125430 points

    The debounce logic runs off the 32k clock (SYSCLK18), which is different than the logic in the rest of the GPIO peripheral.  I recommend looking into your SYSCLK18 configuration, i.e. do you have an external 32k crystal and have you configured CM_SYSCLK18_CLKSEL accordingly.

  • 0 in reply to Brad Griffis
    Prodigy 110 points

    Dear Brad,

    We don't have 32KHz crystal mounted as i have mentioned in my earlier post. We have set CM_SYSCLK18_CLKSEL register to 1, which makes it to use internal audio PLL 32KHz clock as SYSCLK18. Do you foresee any other register settings that we may be missing related to SYSCLK18?

    Dear Pavel,

    We are using DM816x EZSDK 5.05.02.00.

    Regards,

    Sachin

  • 0 in reply to Sachin G Anvekar1
    TI__Guru**** 170625 points

    Sachin,

    Sachin G Anvekar1 said:
    We don't have 32KHz crystal mounted as i have mentioned in my earlier post. We have set CM_SYSCLK18_CLKSEL register to 1, which makes it to use internal audio PLL 32KHz clock as SYSCLK18.

    By default, CM_SYSCLK18_CLKSEL[0] CLKSEL = 0, thus we have:

    ./sys_32k_ck/sysclk18_ck/gpio1_dbck:
    ./sys_32k_ck/sysclk18_ck/gpio2_dbck:

    When I change CM_SYSCLK18_CLKSEL[0] CLKSEL = 1 (in u-boot), I have in lunux kernel:

    ./audio_pll_clk1_ck/audio_pll_a_ck/sysclk18_ck/gpio1_dbck:
    ./audio_pll_clk1_ck/audio_pll_a_ck/sysclk18_ck/gpio2_dbck:

    root@dm816x-evm:/sys/kernel/debug/clock/audio_pll_clk1_ck/audio_pll_a_ck/sysclk18_ck/gpio1_dbck# cat rate
    32768

    Could you check you have the same at your side? You can refer to the TI81xx Clock Framework for more details.

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

    Sachin G Anvekar1 said:
    Do you foresee any other register settings that we may be missing related to SYSCLK18?

    Can you try with:

    CM_ALWON_GPIO_0_CLKCTRL[8] OPTFCLKEN_DBCLK = 1

    CM_ALWON_GPIO_1_CLKCTRL[8] OPTFCLKEN_DBCLK = 1

    See the below e2e thread for more info:

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/217327.aspx

    Regards,
    Pavel