I'm having reliably issues generating a second host (Win 7 PC) MSI interrupt from code running on the DSP side of a DM8147 acting as a PCIe EP.
I have many PCIe bus mastered transactions working successfully. This is a audio device and the "host" is a Windows PC.
- MSI interrupt on completion of sample processing
- EDMA from DSP memory space to host memory for incoming audio samples
- EDMA from host memory to DSP memory for outgoing audio samples
- EDMA metering information from DSP memory to host memory
- interrupt from host to DSP to signal a message should be processed
- EDMA message from the host to DSP internal memory
All of the above work correctly. The issue is that after the last step, the EDMA from host to DSP internal memory, the DSP processes the message, EDMAs the response buffer to host memory, and then is supposed to interrupt the host via an MSI interrupt. This interrupt from the DSP to the host fails to be "seen" by the host about 25% percent of the time. The sample transfer uses MSI interrupt #0 and the response uses MSI interrupt #1. The interrupt is generated by going
HWREG(msi_generate_adr) = msi_generate_data + interrupt_number
and the msi_generate_adr is mapped to the host address space using OB region 0.
The confusing thing is so much seems to working. To have an intermittent issue like this is strange. I assume PCIe transactions can never be lost in way? What are the rules if 2 threads do back to back writes to msi_generate_adr? Is there a way to check a PCIe transaction has completed successfully?
Comments? Suggestions?
