SPI boot error when I put the .text into MSMCSRAM

Feng

Expert 2985 points

Hi TI Experts,

*********************************************************************************

My situation: C6670, CCSV5.3

*********************************************************************************

In my board, the C6670 connects with FPGA through SPI. I just generate the .bin file and load the .bin file into FPGA.

When C6670 is powered up under SPI master boot, C6670 read the .bin file from FPGA through SPI interface.

So the FPGA just simulates a SPI flash.

*********************************************************************************

My testing project is 7612.GPIO_test.zip

The main codes are below

#include <stdio.h>
#include <string.h>
#include <c6x.h>
#include <stdlib.h>

#include "csl_gpio.h"
#include "csl_gpioAux.h"
#include <csl_psc.h>
#include <csl_pscAux.h>
#include "csl_tsc.h"
#include "csl_chip.h"
#include "csl_chipAux.h"
#include "csl_semAux.h"
#include "cslr_device.h"
#include "cslr_psc.h"
#include "csl_psc.h"

extern volatile unsigned int cregister TSCL;

CSL_GpioHandle 		CSL_GPIO_open 		(int instNum);
void 				cycleDelay 			(uint32_t count);

extern void MulticoreBoot();

int main(void)
{
    int i=0;
    char * send_msg;
    int coreId = 0;
    CSL_GpioHandle hGpio;

	//*****************************************************//
	//Boot test
    MulticoreBoot();
    //*****************************************************//

    //*****************************************************//
	//BBU GPIO test
    coreId = DNUM;
    TSCL = 1;
	hGpio = CSL_GPIO_open (0);
	CSL_GPIO_setPinDirOutput(hGpio, 14);
	CSL_GPIO_setPinDirOutput(hGpio, 15);
	if(coreId == 0)
	{
		CSL_GPIO_setOutputData(hGpio,14);
		CSL_GPIO_setOutputData(hGpio,15);
		while(1)
		{
			cycleDelay(1000000000);
			CSL_GPIO_setOutputData(hGpio,14);
			cycleDelay(1000000000);
			CSL_GPIO_clearOutputData(hGpio,14);
		}
	}
	else if(coreId == 1)
	{
		while(1)
		{
			cycleDelay(100000000);
			CSL_GPIO_setOutputData(hGpio,15);
			cycleDelay(100000000);
			CSL_GPIO_clearOutputData(hGpio,15);
		}
	}
	//*****************************************************//

	while(1);
	return 0;
}

CSL_GpioHandle CSL_GPIO_open (int instNum)
{
    if (instNum == 0)
        return (CSL_GpioHandle) CSL_GPIO_REGS;

    /* Control comes here implies that an invalid instance number was passed */
    return (CSL_GpioHandle) 0;
}

void cycleDelay (uint32_t count)
{
  uint32_t sat;

  if (count <= 0)
    return;

  sat = TSCL + count;
  while (TSCL < sat);
}

In this project, the Core0 controls the GPIO15 to blink one LED and the Core1 controls the GPIO14 to blink the other LED.

The MulticoreBoot code is below

#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <ti/csl/csl_chip.h>

#define CORE_NUM_6670     4

void MulticoreBoot()
{

    int *pBootMagicAddCore0;
    int *IpcGr0;
    int i;
    int coreId = 0;

    coreId = DNUM;

	if(coreId == 0)
	{
	   /*write Boot Magic add of other cores and send IPC interrupt*/
		*((int *)(0x118FFFFC)) = 0x0c0008a0;
		*((int *)(0x128FFFFC)) = 0x0c0008a0;
		*((int *)(0x138FFFFC)) = 0x0c0008a0;

	   IpcGr0  = (int*)0x02620240;
	   /*warning:when running on no-boot mode,core0~core7 must all be connected to the target*/
	   for(i = 1;i < CORE_NUM_6670;i++)//core0 sent ipc interrupt to
	   {
		  *(IpcGr0+i) = (*(IpcGr0+i)) | 0x00000001;
	   }
	}
}

The Core0 runs the MulticoreBoot func to write the _c_int00 into Core1's Black Magic Address.

*********************************************************************************

If I put the .text into the per core's L2SRAM like below showing in CMD file

.text > CORE0_L2_SRAM

and then generate the .bin file. The Core0 and Core1 can run OK.

*********************************************************************************

But if I put the .text into the MSMCSRAM like below showing in CMD file

.text > SHRAM

and then generate the .bin file. The Core0 can run but the Core1 can not run OK.

My bin file generating tool is 3884.dsp_SPITool.zip

So what's the difference? And what should I do next?

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I suppose that maybe the Core0 can not write the _c_int00 into Core1's Black Magic Address.

For test, I modify the MulticoreBoot code like below

*((int *)(0x118FFFFC)) = 0x12345678;

But I can not find the number string 12345678 in Core0 project's .out or .bin files!

Is this the key to solve this issue?

*********************************************************************************

Thanks for any replies!

Regards,

Feng

over 10 years ago

0 Feng over 10 years ago

Expert 2985 points

To add some information:

If I put Core0's .text into MSMCSRAM and put Core1's .text into Core1's L2SRAM, Core0 and Core1 can boot up OK.

But if I put Core0's .text into Core0's L2SRAM and put Core1's .text into MSMCSRAM, only Core0 can boot up OK.

0 Raja over 10 years ago in reply to Feng

TI__Guru* 81335 points

Hi Feng,

Apologize for the delayed response. Are you working on EVM or Custom Board? Have you solved the reported issue?

Thank you.

0 Feng over 10 years ago in reply to Raja

Expert 2985 points

Hi Rajasekaran ,

Thank you for your replies firstly!

I am working on my custom board. Actually, in my board I load the boot table file(.bin) into the FLASH connecting to FPGA. When the C6670 is powered up, it works on SPI master boot and read the boot table file(.bin) from FPGA through SPI interface between FPGA and DSP. That is the FPGA simulates a SPI FLASH.

As I mentioned above, if I put the .text into SHRAM, which means that all the 4 cores use the same physical memory section in MSMCSRAM for .text, only Core0 can boot up and the Core1~Core3 will fail.

But in this situation, if I modify the MulticoreBoot like this

#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <ti/csl/csl_chip.h>

#define CORE_NUM_6670     4

void MulticoreBoot()
{

    int *pBootMagicAddCore0;
    int *IpcGr0;
    int i;
    int coreId = 0;

    coreId = DNUM;

    if(coreId == 0)
    {
       /*write Boot Magic add of other cores and send IPC interrupt*/
        *((int *)(0x118FFFFC)) = 0x0c0008a0;
       IpcGr0  = (int*)0x02620244;
       *(IpcGr0+i) = (*(IpcGr0+i)) | 0x00000001;

    }
    else if(coreId == 1)
    {
        *((int *)(0x128FFFFC)) = 0x0c0008a0;
        IpcGr0  = (int*)0x02620248;
       *(IpcGr0+i) = (*(IpcGr0+i)) | 0x00000001;
    }
    else if(coreId == 2)
    {
        *((int *)(0x138FFFFC)) = 0x0c0008a0;
        IpcGr0  = (int*)0x0262024C;
       *(IpcGr0+i) = (*(IpcGr0+i)) | 0x00000001;
    }
}

Which means that after Core0 boots up, it will wake up Core1. After Core1 boots up, it will wake up Core2. After Core2 boots up, it will wake up Core3

And all the cores can boot up! But I do not know why!

Actually, the code above do not contain SYS/BIOS. If I use the SYS/BIOS on each core and put the .text into MSMCSRAM(4 cores use the same physical section for .text), more problems come out!!

I will sum all the problems and launch a new thread for help!

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SPI boot error when I put the .text into MSMCSRAM