Enabling error interrupts on BCP

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Please provide the DSP Part you are using.

Hi,

thanks for the reply.i am using 6670 evm

Hi Jagadeesh,

1. Are you writing to the BCP INTERRUPT RAW STATUS register (INTR_IRS_X, X=coreId) to clear the interrupt or the BCP INTERRUPT CLEAR RAW STATUS register (INTR_IRS_CLR_X, X=coreId)? You need to write to the latter to clear the corresponding sub-module interrupt in INTR_IRS_X.

2. I've attached an example to demostrate BCP error interrupt handling. The example uses a pre-formed HSUPA test packet which has an error in the Rate Dematcher configuration. The packet is sent 10 times and as part of servicing the interrupt, the ISR increments an interrupt counter which is displayed in the console logs. The function register_bcp_error_isr() sets up the error ISR and bcp_error_intr_isr() handles the error (test_common.c).

Please go through ReadMe.txt in the attached zip file to get the build instructions.

Regards
-Nitin

Hi Nitin Sakhuja,

Thank you for the reply. yes I am writing into BCP INTERRUPT CLEAR RAW STATUS register to clear the error in  corresponding sub module. I have gone through the example project given by you. In my project also the BCP module is setting error every time(I have explained it below in steps how I had confirmed it) but my ISR is being hit only for the first time and never there after.

1.i have initialized the packet with invalid sub module ID(14),as a result I got the error and my ISR is being hit.

2.Now I am clearing the ERROR by writing into the clear registers of the corresponding core(I can see it clearing in the memory browser) in my ISR.

3.now for the second time after sending through BCP I can see the ERROR register being set again by BCP(in memory browser), but my ISR is not being hit this time.

4.after the above step I have cleared the ERROR registers manually(by writing into the memory mapped registers.  don't know whether this is the right way or not) since my ISR which is should clear it is not being called for the second time.

5.Now for the third time I am sending through BCP.  and again I could see that BCP is setting the ERROR but my ISR is not being called.

6.i have repeated steps 4 to 5 many times but ISR is not being hit.

As of my understanding there seems no problem with BCP procedure since it is setting the error every time. but i am not understanding why the ISR is not being called every time. are there any other registers need to be cleared in the ISR? i was struck with it. any idea/suggestion would greatly help me. awaiting your reply. thank you

BR,

jagadeesh mavudi

Hello,Can someone help me in this...???

Hi Jagadeesh,

The example provided earlier services the BCP error interrupt 10 times which you can verify by putting a breakpoint in the ISR. Did you try to run it on your EVM?

In your own code, are you using the CpIntc and EventCombiner interrupt dispatch routines as given in the example? If not, then you need to clear and re-enable the system event everytime (using CSL_CPINTC_clearSysInterrupt and CSL_CPINTC_enableSysInterrupt functions) failing which you'll run into the problem you described. Without looking into your code, this is one possibility I can think of. The ISR registration code given below (from my example) avoids this by using the CpIntc_dispatch and EventCombiner funcions which handle this part automatically.

Void register_bcp_error_isr(Uint32 coreId)
{
    static UInt32 cookie    = 0;
    Uint32 gemEventId       = 0;

    /* Disable global interrupts */
    cookie = Hwi_disable();

    /* ISR Registration */
    CpIntc_dispatchPlug(BCP_ERROR_SYS_EVTID(coreId), bcp_error_intr_isr, coreId, TRUE);
    CpIntc_mapSysIntToHostInt(0, BCP_ERROR_SYS_EVTID(coreId), BCP_ERROR_HOST_EVTID(coreId));
    CpIntc_enableHostInt(0, BCP_ERROR_HOST_EVTID(coreId));
    gemEventId = CpIntc_getEventId(BCP_ERROR_HOST_EVTID(coreId));
    EventCombiner_dispatchPlug (gemEventId,
                                CpIntc_dispatch,
                                BCP_ERROR_HOST_EVTID(coreId),
                                TRUE);

    /* enable the 'global' switch */
    CpIntc_enableAllHostInts(0);

    /* Restore interrupts */
    Hwi_restore(cookie);
}        

We'll need your ISR regstration and handler code to comment on this further but I would suggest you to run the example on your EVM and use that as a reference.

Regards
-Nitin

Hi Nitin,

thanks a lot. that has solved my problem on 6670 EVM, but i am facing the same problem when implementing on 6614. on 6670, BCP error was listed in secondary event table hence the use of CPINTC is justified, but on 6614 BCP error was listed in primary events table so i have hooked my ISR to event number 65 on 6614 ( primary interrupt table pg.no 176,TMS320TCI6614 Communications Infrastructure KeyStone SoC, Literature Number: SPRS671D ) in CFG file. when encountering error in BCP the ISR has been hit for the first time but never then after, but BCP is setting error every time. i think CPINTC has no role on this since the event is a primary event. is that true? any suggestion in this regard ?

the piece of code in CFG file for ISR is shown below:

var instti_sysbios_Hwi1Params1 = new ti_sysbios_Hwi.Params() ;

instti_sysbios_Hwi1Params1.eventId = 65 ;

instti_sysbios_Hwi1Params1.instance.name="HWI_BCP" ;

Program.global.HWI_BCP = ti_sysbios_Hwi.create(10, BCP_error_int_isr",ti_sysbios_Hwi1Params1);

Hi Nitin,

I have implemented the same that you have provided me. but it still didn't solve my problem. the ISR is still not being hit after the first time.is there any other dimension to look into it?

thank you.

Hi Jagadeesh,

Please use the attached example as a reference on Appleton EVM. I modified my original 6670 example for Appleton and apart from the PSC related changes in test_main.c, the only other change is in the ISR setup function as I mentioned yesterday. It also uses Appleton PDK so make sure you have that installed on your system. The error interrupt is serviced 10 times as before.

Regards
-Nitin