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OMAP2530 McBSP Full Duplex Mode

Jonathan Tate
Intellectual 1745 points
Other Parts Discussed in Thread: SYSCONFIG

My customer is unable to get the McBSP to work in full duplex mode. It works fine if one side is configured as a transmitter and the other as a receiver, but it won't work if both are configured as both transmitter and receiver.

CLKX and CLKR are divided down to 1MHz

They have McBSP1 tied together between two processors with the following connections:

Thanks for the help

 

 

  • 0
    TI__Mastermind 29095 points

    Can you get more details on the configuration? a register dump perhaps?

    On both processors, the transmitter should configured as a master and the receiver as a slave - This allows the transmitter to only generate a frame sync when there is data to send. Frame, word size, etc should be the same on both processors.

    BRs

      Paul

     

     

  • 0 in reply to PaulM
    TI__Intellectual 1745 points

    Here is more info, let me know if I need to get add’l information:

    believe I have the transmitter configured as Master and the receiver as Slave.

    Here is a dump of the various McBSP registers:

    CONTROL_DEVCONF0: 04000018
    CONTROL_DEVCONF1: 002FFF80
    MCBSP1_DRR_REG: FEFFFFFF
    MCBSP1_DXR_REG: 00000000
    MCBSP1_SPCR2_REG: 00000083
    MCBSP1_SPCR1_REG: 00000001
    MCBSP1_RCR2_REG: 00000000
    MCBSP1_RCR1_REG: 000000A0
    MCBSP1_XCR2_REG: 00000000
    MCBSP1_XCR1_REG: 000000A0
    MCBSP1_SRGR2_REG: 00002040
    MCBSP1_SRGR1_REG: 00000001
    MCBSP1_MCR2_REG: 00000000
    MCBSP1_MCR1_REG: 00000000
    MCBSP1_RCERA_REG: 00000000
    MCBSP1_RCERB_REG: 00000000
    MCBSP1_XCERA_REG: 00000000
    MCBSP1_XCERB_REG: 00000000
    MCBSP1_PCR_REG: 00000080
    MCBSP1_RCERC_REG: 00000000
    MCBSP1_RCERD_REG: 00000000
    MCBSP1_XCERC_REG: 00000000
    MCBSP1_XCERD_REG: 00000000
    MCBSP1_RCERE_REG: 00000000
    MCBSP1_RCERF_REG: 00000000
    MCBSP1_XCERE_REG: 00000000
    MCBSP1_XCERF_REG: 00000000
    MCBSP1_RCERG_REG: 00000000
    MCBSP1_RCERH_REG: 00000000
    MCBSP1_XCERG_REG: 00000000
    MCBSP1_XCERH_REG: 00000000
    MCBSP1_REV_REG: 00000021
    MCBSP1_RINTCLR_REG: 00000000
    MCBSP1_XINTCLR_REG: 00000000
    MCBSP1_ROVFLCLR_REG: 00000000
    MCBSP1_SYSCONFIG_REG: 00000000
    MCBSP1_THRSH2_REG: 00000000
    MCBSP1_THRSH1_REG: 00000000
    MCBSP1_IRQSTATUS_REG: 00000410
    MCBSP1_IRQENABLE_REG: 00000000
    MCBSP1_WAKEUPEN_REG: 00000000
    MCBSP1_XCCR_REG: 00001008
    MCBSP1_RCCR_REG: 00000008
    MCBSP1_XBUFFSTAT_REG: 00000080
    MCBSP1_RBUFFSTAT_REG: 00000000

  • 0 in reply to Jonathan Tate
    TI__Mastermind 29095 points

    Jonathan

     

    The CONTROL_DEVCONF0 is current configured for 4 pin mode. This needs to be changes to 6 pin mode:

     

    CONTROL_DEVCONF0.MCBSP1_CLKR SHOULD = 0

    CONTROL_DEVCONF0.MCBSP1_FSR SHOULD = 0

     

     

    I see the Frame period is set to 65 bits (SRGR2_REG) with only 1 32bit word per frame. It would be more efficient to match the actual number of bits transmitted/received in a frame.

     

    Since the transmitter is the master, the SRG needs a running clock source. Using the mcbsp1_clkx to generate CLKG to feed mcbsp1_clkx CLKX will not work. There are several configurations you can use.

     

    Both masters could use an internal clock (FCLK or iCLK)

    Both masters could be clocked externally through the mcbsp_clks pin.

     

    Alternately, one master could use any of the above clock sources, and feed the second master a clock through the mcbsp1_clkr pin or the mcbsp_clks pin. Note mcbsp_clks pin is common to all mcbsp modules. 

     

     

    The PCR_REG.CLKXM and PCR_REG.FSXM should both = 1. This will enable them as output signals.

     

    I see the RCCR_REG.RFULL_CYCLE=0. Since the transmitter master is configured to transmit on the rising edge, it is safer to sample FSX on the falling edge. Therefore RCCR_REG.RFULL_CYCLE should be left in it’s reset state (1).

     

    Finally, make sure the padconf register for the McBSP1 pins are configured correctly. All pins should have the input enabled with the exception of mcbsp1_dx.

     

      Paul