My architecture: I'm running on an OMAP L138. I have 15MB of DDR used for SysLink region 0, and the next 1MB of DDR used for slow DSP code/data. The L3 shared region is assigned to SysLink region 1, from which I allocate a shared data structure at startup for the ARM and DSP to talk over. IPC Notify triggers the DSP to do stuff with that data, and tells the ARM when the DSP is finished with a command.
Commands happen infrequently, and can be processed fairly slowly (compared to the hard-real-time DSP). I'd like to keep the slow command handling out of cache where possible - I know this isn't possible for program, but it should be for data. This should minimise cache rewriting for the faster data used by the processing loop.
For both these sections, I have tried using the MAR registers to disable caching for that block of memory and setting "enableCaching" to false in the SharedRegion configuration. The result is that the code runs until it gets a command, at which point the DSP hangs. This is true for disabling caching for either region individually or both together. When I say "hang", it's clearly hanging in a HWI or a very-high-priority SWI, because the periodic SWI (Clock) which toggles a heartbeat LED stops. Unfortunately I don't think I can get a debugger on it (unless there's some kind of DSP debugging possible via the ARM over telnet?) so I can't be more specific than that.
If I keep caching enabled for both, it works perfectly (as it has done for the last year - in case it's not clear, I'm trying to squeeze maximum performance out of an existing architecture).
Apart from the cache MAR and the SharedRegion "enableCaching" flag, is there anything else I should be setting up to do this? Or have I missed some crucial concept here which means this is never going to work?
