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AM335x UART0 DMA

Steve Schefter
Expert 1780 points

Hi.

I am able to use DMA for receive with UART ports 1 and up, but not UART0.  For UART0, the received data remains in the UART FIFO and no DMA request is made.

There are two ways to enable DMA mode in the UART.  First, DMA_MODE in FCR.  Second, setting DMAMODECTL and DMAMODE2 in SCR.  I've tried both and see the same result.

UART0 seems to be a special case as its attributes are listed in a separate chart in the TRM.  Is there anything different about initializing UART0 DMA than the other ports?

Thanks,

     Steve

  • 0
    TI__Guru**** 393215 points

    Hi Steve,

    What software are you using? UART0 is normally used for debug console in Linux.

  • 0 in reply to Biser Gatchev-XID
    Expert 1780 points

    Hi Biser.

    I am using Linux -- TI's 3.2 kernel.

    Unfortunately, this board has UART0 wired with a serial connection to a DSP while it's UART4 that's the console.  Because of the data rate involved, DMA is needed for the connection to the DSP.

    A previous board running the same kernel had UART1 for the connection to the DSP and I was able to use DMA.  That's why I'm wondering if there's something different about UART0.

    Regards,

         Steve

  • 0 in reply to Steve Schefter
    Expert 1780 points

    Hi Biser.

    A bit more detail:

    When using SCR to enable DMA, I see the following register values after a timeout waiting for the DMA to transfer data:

                     UART LSR 0x61  --  indicating "At least one data character in the RX FIFO"
                     UART SCR 0xCB -- indicating "The DMAMODE is set with SCR" and DMA Mode 1 is selected
                     DMA EER0 0x0A000000  -- indicating that channel 27 (UART0 RXDMA) is enabled
                     DMA ER0  0x04000000  -- indicating that no DMA event has been generated for channel 27

    So while there is a receive character available, it appears as though the UART is not asserting the DMA request.

    Regards,

                    Steve

  • 0 in reply to Steve Schefter
    TI__Guru**** 393215 points

    The only difference I see for UART0 is in the 19.5.1.43 SYSC Register bits 4:3 (section 19.5.1.43 in the AM335X TRM Rev. K)

  • 0 in reply to Biser Gatchev-XID
    Expert 1780 points

    Hi Biser.

    This problem isn't related to wakeup.  The problem occurs right from boot, before the device suspends.

    I am beginning to wonder if the UART0/DMA connection was ever validated in the AM335x.  Unfortunately, with it being an internal signal, I can't measure it.  I can only see the status registers which seem to indicate that UART0 isn't asserting that the way other UARTs do.

    Regards,

         Steve

  • 0 in reply to Steve Schefter
    Expert 1780 points

    Hi Biser.

    One further note on this.  If I, after a timeout, write to the EDMA Event Set Register (ESR) to manually set an event for the channel, the DMA transfer from the UART to memory occurs as expected. But just one byte is transferred, even though there are several bytes in the receive FIFO.

    Regards,
          Steve