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J6 Eco with Spread Spectrum clocking

K Md Feroz Irfan
Expert 7225 points

Dear All,

Request your inputs here for below customer query. Basically do we have any information or test data of the performance of J6 Eco with Spread Spectrum clocking ? Has it been any time implemented ?

 I would like to know more about the Clock & Timing solution by Spread Spectrum Clocking (SSC) from Ti

 

Target processor:  J6 Eco

 

Clocks:

HF clocks (MHz)

 

20 MHz – To Processor

22.5792 MHz- To Processor

25MHz - To EMAC PHY (2 numbers)

LF Clock (KHz)

 

32.968 KHz- To Processor

 

The current plan is using dedicated AECQ crystals similar like EVM

 

Please let me know your thoughts on Spread Spectrum Oscillator approach

Share the Pros & Cons of the approach. Expecting few implementation details & statistical data by SSC approach in J6 Eco/OMAP5 core 

Best Regards,

Feroz

  • 0
    TI__Guru**** 161600 points

    Hi Feroz,

    To my knowledge SSC feature is not supported for J6/J6Eco devices. If have a look at Table 11-48. PLL_SSC_CONFIGURATION1 in DRA75x_74x TRM, you'll see that in the description of the register, there is a note:
    "Configuration for PLL Spread Spectrum Clocking modulation.
    Note: SSC feature is not supported."
    Same description is valid for DRA72x devices.

    AFAIK, SSC feature was never validated.

    If you need further details please post in the INTERNAL section of the e2e forum, because documentation about J6/J6Eco is NDA and cannot be discussed in a public forum.

    Best Regards,
    Yordan