24Mhz clk from ATL_CLKOUT0/ATL_CLKOUT1

Manoj,

selvam mk said:

I'm using DM38x with EZSDK

With DM814x EZSDK 5.05.02.00 ?

selvam mk said:

i want to generate 24Mhz clk from ATL_CLKOUT0/ATL_CLKOUT1 pin out

What is the default/current frequency on the ATL_CLKOUT0/1 pin out? What is the functional clock input frequency (atl_fck)? What is the interconnect clock input frequency (atl_ick)?

The ATL module func input clock (atl_fck) can be sourced from sysclk19, DPLL_AUDIO or DPLL_VIDEO0/1/2 selected in MLB_ATL_CLKSRC[17:16] ATL_SOURCE

In DM814x EZSDK 5.05.02.00 by default we have:

osc0_clkin_ck -> iss_dpll_ck -> iss_dpll_d2_ck -> audio_dpll_clk2 -> sysclk19_ck -> atl_fck, which means that sysclk19 is the source and the frequency of the atl_fck is 200MHz.

osc0_clkin_ck -> l3_dpll_clkin_ck -> l3_dpll_ck -> sysclk4_ck -> sysclk6_ck -> atl_ick, the frequency is 100MHz.

Refer to the below resources:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

linux-kernel/arch/arm/mach-omap2/clock814x_data.c

/* ATL OCP Clock(final) */
static struct clk atl_ick = {
    .name        = "atl_ick",
    .parent        = &sysclk6_ck,
    .ops        = &clkops_null,
    .clkdm_name    = "alwon_l3_slow_clkdm",
    .recalc        = &followparent_recalc,
};

static const struct clksel atlp_clk_mux_sel[] = {
    { .parent = &sysclk19_ck, .rates = div_1_0_rates },
    { .parent = &audio_dpll_ck, .rates = div_1_1_rates },
    { .parent = &video012_dpll_muxout_ck, .rates = div_1_2_rates },
    { .parent = NULL}
};

/* atl pclk (MUX out) */
static struct clk atl_fck = {
    .name        = "atl_fck",
    .init        = &omap2_init_clksel_parent,
    .ops        = &clkops_ti81xx_dflt_wait,
    .enable_reg    = TI814X_CM_ALWON_ATL_CLKCTRL,
    .enable_bit    = TI81XX_MODULEMODE_SWCTRL,
    .clksel        = atlp_clk_mux_sel,
    .clksel_reg    = TI814X_PLL_CMGC_MLB_ATL_CLKSRC,
    .clksel_mask    = TI814X_MLB_ATL_ATL_MASK,
    .clkdm_name    = "alwon_l3_slow_clkdm",
    .recalc        = &omap2_clksel_recalc,
};

DM38x TRM, PRCM and ATL chapters

Regards,
Pavel

Hi Pavel,

I'm using EZSDK 5.05.02.00, atl_fck and atl_ick are at default value.

By default i'm not getting any clock on ATL_CLKOUT0/1 pin.

There are only to register  for ATL settings on TRM, CM_ALWON_ATL_CLKCTRL, and ATL_CLKSRC.

I did the following changes,

1. for ATL_CLKOUT0 pin Mux  0x48140834 ==> 00000002.
2. CM_ALWON_ATL_CLKCTRL 0x48181570 ==> 00000002.

3. ATL_CLKSRC 0x481c52cc ==> 00000000.

Still no output on ATL_CLKOUT0 pin.

Please correct me if i'm doing some thing wrong.

Regards,

Manoj

Manoj,

selvam mk said:

1. for ATL_CLKOUT0 pin Mux  0x48140834 ==> 00000002.

From the DM385/DM388 datasheet I see that you should configure ATL_CLKOUT0 like
PINCNTL14/0x48140834 = 0x000C0020 (not 0x00000002)

selvam mk said:

2. CM_ALWON_ATL_CLKCTRL 0x48181570 ==> 00000002.

Can you check to read a register from the ATL module, thus verify the ATL module is functional after enable the clock.

selvam mk said:

Still no output on ATL_CLKOUT0 pin.

Do you check the AF31 physical pin?

Regards,
Pavel

Hi Pavel,

Thanks for the reply,

Sorry value of 0x48140834 is 0x00000020 not 0x00000002.

Pavel Botev said:

From the DM385/DM388 datasheet I see that you should configure ATL_CLKOUT0 like
PINCNTL14/0x48140834 = 0x000C0020 (not 0x00000002)

even i checked by  changing  the value to 0x000C0020(No output on ATL_CLKOUT0 pin) .

Pavel Botev said:

Can you check to read a register from the ATL module, thus verify the ATL module is functional after enable the clock.

read back value of 0x48181570 is 0x00000002. can you specify which address i want to read?

Pavel Botev said:

Do you check the AF31 physical pin?

yes,

Regards,

Manoj

Manoj,

selvam mk said:

can you specify which address i want to read?

0x481D4000

BR
Pavel

Hi Pavel,

I'm not able read it. getting Bus error.

But in datasheet 0x481D_4000 to 0x481D_5FFF described as Reserved

Regards,

Manoj

Manoj,

selvam mk said:

But in datasheet 0x481D_4000 to 0x481D_5FFF described as Reserved

Yes, but we do not have ATL module base address at all in the DM385/DM388 datasheet! In DM811x device ATL base address is on 0x481D4000.

Let me check with the DM385 team if ATL module exist in DM38x device and if yes, what is the base address.

Regards,
Pavel

Hi Pavel,

On DM385

Value of 481d400 is 0A070100, earlier error was on DM383.

Still i want to get clk from ATL_CLKOUT0.

Regards,

Manoj

Manoj,

selvam mk said:

On DM385

Value of 481d400 is 0A070100

So, when you have CM_ALWON_ATL_CLKCTRL[1:0] MODULEMODE = 0x0, when you try to read DM385 register 0x481D4000, you are not able to read it, you have bus error. But when have CM_ALWON_ATL_CLKCTRL[1:0] MODULEMODE = 0x2, you are able to read DM385 register 0x481D4000 successful. Is this correct?

Can you provide me the values of the below registers:

0x481D4200

0x481D4204

0x481D4208

0x481D4210

0x481D4214

0x481D4218

0x481D421C

Regards,
Pavel

Hi Pavel,

Value of CM_ALWON_ATL_CLKCTRL[1:0] MODULEMODE is always 0x2.

We have DM383 and DM385, when i tried to read 0x481D4000 on DM383 i used to get Bus error

Please find the values for the above registers on DM385,

0x481D4200 : 0x00000000

0x481D4204 : 0x00000000

0x481D4208 : 0x00000018

0x481D4210 : 0x00000000

0x481D4214 : 0x00000000

0x481D4218 : 0x00000000

0x481D421C : 0x00000000

Regards,

Manoj

Manoj,

selvam mk said:

Value of CM_ALWON_ATL_CLKCTRL[1:0] MODULEMODE is always 0x2.

We have DM383 and DM385, when i tried to read 0x481D4000 on DM383 i used to get Bus error

For DM385 device, can you clear bits  CM_ALWON_ATL_CLKCTRL[1:0] MODULEMODE = 0x0, then would you be able to read 0x481D4000 ?

BR
Pavel

Manoj,

selvam mk said:

0x481D4210 : 0x00000000

Can you try setting bit [0] of the 0x481D210 register to 1 (SWEN0[0] SWEN = 1). Is this new value accepted, I mean can you read then the new value (0x00000001)? If yes, can you try measure the ATL_CLKOUT0 pin frequency, do you have any value now?

BR
Pavel

Hi Pavel,

Pavel Botev said:

For DM385 device, can you clear bits  CM_ALWON_ATL_CLKCTRL[1:0] MODULEMODE = 0x0, then would you be able to read 0x481D4000 ?

No

Pavel Botev said:

Can you try setting bit [0] of the 0x481D210 register to 1 (SWEN0[0] SWEN = 1). Is this new value accepted, I mean can you read then the new value (0x00000001)?

Yes,

Pavel Botev said:

can you try measure the ATL_CLKOUT0 pin frequency, do you have any value now?

yes, 4Mhz square wave.

Regards,

Manoj

Pavel,

Can you give me the ATL module datasheet or register settings to generate 24Mhz clk. ?

Regards,

Manoj

Manoj,

Can you try set bit [0] of register at address 0x481D421C to 0x1 (PCLKMUX0[0] PCLKMUX = 1), what is the ATL_CLKOUT0 freq then?

BR
Pavel

Hi Pavel,

Pavel Botev said:

Can you try set bit [0] of register at address 0x481D421C to 0x1 (PCLKMUX0[0] PCLKMUX = 1)

No, when i tried to set the bit[0] of 481d421c system hangs and system reset is the only recovery for this.

Regards,

Manoj

Manoj,

Then I am not sure if it is possible to generate 24Mhz from the ATL module. I will check with the ATL expert and let you know when I have something.

Regards,
Pavel

Hi Pavel,

Can you please conform the availability of ATL module in DM383.

Regards,

Manoj