Hi,
I want to use SPI in edma mode. Not in linux ,but bios. The edma have verfiyed OK by move memory from one space to another space. And also the SPI work OK without edma. But if i use the spi with edma, the edma completion isr be touched, but the I can not see any wave at spi port. The code is below:
Thanks
the spi function
{
spi_regs = handle->spi_regs;
/* Reset SPI */
spi_regs->SPI_SYSCONFIG |= 0x02; // Bit is automatically reset by hardware
/* Wait for reset to complete */
while(spi_regs->SPI_SYSSTATUS & 0x01 == 0x00);
spi_regs->SPI_SYSCONFIG = 0x15;
/* Configure MCSPI Module */
spi_regs->SPI_MODULCTRL = 0
| ( 0 << 8 ) // Data managed by MCSPI_TX(i) and MCSPI_RX(i) registers
| ( 0 << 7 ) // Multiple word access disabled
| ( 0 << 4 ) // No delay for first spi transfer
| ( 0 << 3 ) // Functional mode
| ( 0 << 2 ) // Master
| ( 0 << 1 ) // SPIEN is used as a chip select
| ( 1 << 0 );// Only one channel will be used in master mode
/* Configure MCSPI Channel 0 */
spi_regs->SPI_CH0CONF = 0
| ( 0 << 29 ) // Clock divider granularity of power of two
| ( 0 << 28 ) // The buffer is used to receive data Antimax no use
| ( 0 << 27 ) // The buffer is used to transmit data Antimax no use
| ( 1 << 25 ) // 1.5 cycles between CS toggling and first or last edge of SPI clock
| ( 0 << 24 ) // Start bit polarity
| ( 0 << 23 ) // Disable start bit
| ( 0 << 20 ) // SPIEN active between SPI words
| ( 0 << 19 ) // Turbo is deactivated
| ( 0 << 18 ) // Data Line0 selected for reception
| ( 0 << 17 ) // Data Line1 selected for transmission
| ( 1 << 16 ) // No transmission on Data Line0
| ( 0 << 15 ) // DMA Read Request disabled
| ( 0 << 14 ) // DMA Write Request disabled
| ( 2 << 12 ) // Transmit mode
| ( 7 << 7 ) // SPI word length = 8
| ( 1 << 6 ) // SPIEN is held high during the active state
| ( 8 << 2 ) // CLKD = 8 Clock devider (Recalibrate according to pll)????????????????????
| ( 0 << 1 ) // SPICLK is held high during the active state
| ( 0 << 0 );// Data are latched on even numbered edges of SPICLK
spi_regs->SPI_WAKEUPENABLE = 1;
/* Enable MCSPI channel */
spi_regs->SPI_MODULCTRL = 0x01; // Enable Channel
/* Enable Channel */
spi_regs->SPI_CH0CTRL = 0x01;
/* SPI access cycle */
spi_regs->SPI_CH0CONF |= 0x00100000;
#if 0
for ( i = 0 ; i < length ; i++ )
{
/* Wait for transmit empty */
while ( (spi_regs->SPI_CH0STAT & 0x02) == 0 );
spi_regs->SPI_TX0 = tx_buf[i]; // Write to RX buffer 0
}
#else
DM81XX_EDMA3_setParams(EDMA_CHN_SPI1XEVT0, EDMA3_TCC1,
(unsigned int) tx_buf,
(unsigned int) spi_regs->SPI_TX0,
length, 1, 0, 0);
DM81XX_EDMA3_triggerTransfer(EDMA_CHN_SPI1XEVT0);
spi_regs->SPI_CH0CONF |= (1 << 14); //DMA Write enable
#endif
spi_regs->SPI_CH0CONF &= ~0x00100000;
/* Disable Channel */
spi_regs->SPI_CH0CTRL = 0x00;
}
the emda function :
void DM81XX_EDMA3_setParams(int chId,
int dmaQueue,
unsigned int srcAddr,
unsigned int dstAddr,
unsigned short edmaWidth,
unsigned short edmaHeight,
short srcLineOffset, short dstLineOffset)
{
edmac_regs = (CSL_EdmaccRegs *)DM81XX_EDMA3_CC_BASE;
/* PaRAM entry setup */
edmac_regs->PARAMENTRY[chId].OPT = ((0) | // SAM ->
//
// INCR
// mode
(0 << 1) | // DAM
//
// ->
// static
// mode
(0 << 2) | // SYNCDIM
//
// ->
// A
// synchronized
(0 << 3) | // STATIC
//
// ->
// non-static
// mode
(0 << 8) | // FWID
//
// ->
// FIFO
// width
// is
// 8
// bits
(0 << 11) | // TCCMODE
//
// ->
// Normal
// completion
(chId << 12) | // TCC
//
// ->
// Transfer
// Completion
// Code
(1 << 20) | // TCINTEN
//
// ->
// Transfer
// Complete
// Interrupt
// is
// enabled
(0 << 21) | // ITCINTEN
//
// ->
// Intermediate
// transfer
// complete
// interrupt
// is
// disabled
(0 << 22) | // TCCHEN
//
// ->
// Transfer
// Complete
// Chaining
// is
// disabled
(0 << 23) | // ITCCHEN
//
// ->
// Intermediate
// transfer
// complete
// chaining
// is
// disabled
(0 << 24)); // PRIVID
//
//
// ->
// Privilege
// identification
// for
// the
// external
// host/CPU/DMA
// that
edmac_regs->PARAMENTRY[chId].SRC = srcAddr;
edmac_regs->PARAMENTRY[chId].A_B_CNT = (edmaHeight << 16) | (edmaWidth);
edmac_regs->PARAMENTRY[chId].DST = dstAddr;
edmac_regs->PARAMENTRY[chId].SRC_DST_BIDX = (dstLineOffset << 16) | (srcLineOffset);
edmac_regs->PARAMENTRY[chId].LINK_BCNTRLD = (0 << 16) | 0xFFFF;
edmac_regs->PARAMENTRY[chId].SRC_DST_CIDX = (0 << 16) | 0;
edmac_regs->PARAMENTRY[chId].CCNT = 1;
if (chId < 32)
{
/* Set Shadow region for the channel */
edmac_regs->DRA[SHADOW_REGION].DRAE |= (1 << chId);
/* Enable interrupt */
edmac_regs->SHADOW[SHADOW_REGION].IESR |= (1 <<chId);
}
else
{
/* Set Shadow region for the channel */
edmac_regs->DRA[SHADOW_REGION].DRAEH |= (1 << (chId - 32));
/* Enable interrupt */
edmac_regs->SHADOW[SHADOW_REGION].IESRH |= (1 << (chId - 32));
}
/* channel to PaRAM entry mapping */
edmac_regs->DCHMAP[chId] = (chId << 5);
// maintainig one
// to one mapping
// between channel
// and PaRAM entry
/* channel to queue mapping */
edmac_regs->DMAQNUM[chId / 8] |= (dmaQueue << ((chId % 8) * 4));
}
void DM81XX_EDMA3_triggerTransfer(int chId)
{
if(chId <32)
{
/* clear the event set */
edmac_regs->SHADOW[SHADOW_REGION].SECR |= (1 << chId);
edmac_regs->EMCR |= (1 << chId);
edmac_regs->SHADOW[SHADOW_REGION].ECR |= (1 << chId);
/* Set event enable */
edmac_regs->SHADOW[SHADOW_REGION].EESR |= (1 << chId);
}
else
{
/* clear the event set */
edmac_regs->SHADOW[SHADOW_REGION].SECRH |= (1 << (chId - 32));
edmac_regs->EMCR |= (1 << (chId - 32));
edmac_regs->SHADOW[SHADOW_REGION].ECRH |= (1 << (chId - 32));
/* Set event enable */
edmac_regs->SHADOW[SHADOW_REGION].EESRH |= (1 << (chId - 32));
}
}
