First off, thank you in advance for taking the time to read this post and offer any help. I am working on a custom board bring up using the AM3359. We are attempting to validation the board design from within u-boot. I have downloaded the ti-sdk 7.00.00.00 and using u-boot-2013.10-ti2013.12.01.
I have used 2.5.2.0 to generate the pinmux example. I incorporated that into the mux.c file located in <u-boot directory>/board/ti/amm335x. The issue that I am having is that i was unable to get the spi0 pins to function for reading an EEPROM located on that bus. I then switched them over to GPIO pins and connected them to a scope. I wanted to demonstrate that I actually had control of the pins. 2 out of the 4 pins did toggle when commanded.
To eliminate a hardware issue, I swapped boards. On this board I was unable to toggle any pins. As of right now I have all of the other muxing disabled so as not to disturb the pin states that I have defined. I was hoping someone may be able to provide me some insight into what I might be doing wrong.
*EDIT - I did update to the latest u-boot and the problem still persists
Below you will find my mux.c source:
/*
* mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
#define CONFIG_CMD_SPI
#define MODE0 0
#define MODE1 1
#define MODE2 2
#define MODE3 3
#define MODE4 4
#define MODE5 5
#define MODE6 6
#define MODE7 7
#define IDIS (0 << 5)
#define IEN (1 << 5)
#define PD (0 << 3)
#define PU (2 << 3)
#define OFF (1 << 3)
/*
* To get the physical address the offset has
* to be added to AM335X_CTRL_BASE
*/
#define CONTROL_PADCONF_GPMC_AD0 0x0800
#define CONTROL_PADCONF_GPMC_AD1 0x0804
#define CONTROL_PADCONF_GPMC_AD2 0x0808
#define CONTROL_PADCONF_GPMC_AD3 0x080C
#define CONTROL_PADCONF_GPMC_AD4 0x0810
#define CONTROL_PADCONF_GPMC_AD5 0x0814
#define CONTROL_PADCONF_GPMC_AD6 0x0818
#define CONTROL_PADCONF_GPMC_AD7 0x081C
#define CONTROL_PADCONF_GPMC_AD8 0x0820
#define CONTROL_PADCONF_GPMC_AD9 0x0824
#define CONTROL_PADCONF_GPMC_AD10 0x0828
#define CONTROL_PADCONF_GPMC_AD11 0x082C
#define CONTROL_PADCONF_GPMC_AD12 0x0830
#define CONTROL_PADCONF_GPMC_AD13 0x0834
#define CONTROL_PADCONF_GPMC_AD14 0x0838
#define CONTROL_PADCONF_GPMC_AD15 0x083C
#define CONTROL_PADCONF_GPMC_A0 0x0840
#define CONTROL_PADCONF_GPMC_A1 0x0844
#define CONTROL_PADCONF_GPMC_A2 0x0848
#define CONTROL_PADCONF_GPMC_A3 0x084C
#define CONTROL_PADCONF_GPMC_A4 0x0850
#define CONTROL_PADCONF_GPMC_A5 0x0854
#define CONTROL_PADCONF_GPMC_A6 0x0858
#define CONTROL_PADCONF_GPMC_A7 0x085C
#define CONTROL_PADCONF_GPMC_A8 0x0860
#define CONTROL_PADCONF_GPMC_A9 0x0864
#define CONTROL_PADCONF_GPMC_A10 0x0868
#define CONTROL_PADCONF_GPMC_A11 0x086C
#define CONTROL_PADCONF_GPMC_WAIT0 0x0870
#define CONTROL_PADCONF_GPMC_WPN 0x0874
#define CONTROL_PADCONF_GPMC_BEN1 0x0878
#define CONTROL_PADCONF_GPMC_CSN0 0x087C
#define CONTROL_PADCONF_GPMC_CSN1 0x0880
#define CONTROL_PADCONF_GPMC_CSN2 0x0884
#define CONTROL_PADCONF_GPMC_CSN3 0x0888
#define CONTROL_PADCONF_GPMC_CLK 0x088C
#define CONTROL_PADCONF_GPMC_ADVN_ALE 0x0890
#define CONTROL_PADCONF_GPMC_OEN_REN 0x0894
#define CONTROL_PADCONF_GPMC_WEN 0x0898
#define CONTROL_PADCONF_GPMC_BEN0_CLE 0x089C
#define CONTROL_PADCONF_LCD_DATA0 0x08A0
#define CONTROL_PADCONF_LCD_DATA1 0x08A4
#define CONTROL_PADCONF_LCD_DATA2 0x08A8
#define CONTROL_PADCONF_LCD_DATA3 0x08AC
#define CONTROL_PADCONF_LCD_DATA4 0x08B0
#define CONTROL_PADCONF_LCD_DATA5 0x08B4
#define CONTROL_PADCONF_LCD_DATA6 0x08B8
#define CONTROL_PADCONF_LCD_DATA7 0x08BC
#define CONTROL_PADCONF_LCD_DATA8 0x08C0
#define CONTROL_PADCONF_LCD_DATA9 0x08C4
#define CONTROL_PADCONF_LCD_DATA10 0x08C8
#define CONTROL_PADCONF_LCD_DATA11 0x08CC
#define CONTROL_PADCONF_LCD_DATA12 0x08D0
#define CONTROL_PADCONF_LCD_DATA13 0x08D4
#define CONTROL_PADCONF_LCD_DATA14 0x08D8
#define CONTROL_PADCONF_LCD_DATA15 0x08DC
#define CONTROL_PADCONF_LCD_VSYNC 0x08E0
#define CONTROL_PADCONF_LCD_HSYNC 0x08E4
#define CONTROL_PADCONF_LCD_PCLK 0x08E8
#define CONTROL_PADCONF_LCD_AC_BIAS_EN 0x08EC
#define CONTROL_PADCONF_MMC0_DAT3 0x08F0
#define CONTROL_PADCONF_MMC0_DAT2 0x08F4
#define CONTROL_PADCONF_MMC0_DAT1 0x08F8
#define CONTROL_PADCONF_MMC0_DAT0 0x08FC
#define CONTROL_PADCONF_MMC0_CLK 0x0900
#define CONTROL_PADCONF_MMC0_CMD 0x0904
#define CONTROL_PADCONF_MII1_COL 0x0908
#define CONTROL_PADCONF_MII1_CRS 0x090C
#define CONTROL_PADCONF_MII1_RX_ER 0x0910
#define CONTROL_PADCONF_MII1_TX_EN 0x0914
#define CONTROL_PADCONF_MII1_RX_DV 0x0918
#define CONTROL_PADCONF_MII1_TXD3 0x091C
#define CONTROL_PADCONF_MII1_TXD2 0x0920
#define CONTROL_PADCONF_MII1_TXD1 0x0924
#define CONTROL_PADCONF_MII1_TXD0 0x0928
#define CONTROL_PADCONF_MII1_TX_CLK 0x092C
#define CONTROL_PADCONF_MII1_RX_CLK 0x0930
#define CONTROL_PADCONF_MII1_RXD3 0x0934
#define CONTROL_PADCONF_MII1_RXD2 0x0938
#define CONTROL_PADCONF_MII1_RXD1 0x093C
#define CONTROL_PADCONF_MII1_RXD0 0x0940
#define CONTROL_PADCONF_RMII1_REF_CLK 0x0944
#define CONTROL_PADCONF_MDIO 0x0948
#define CONTROL_PADCONF_MDC 0x094C
#define CONTROL_PADCONF_SPI0_SCLK 0x0950
#define CONTROL_PADCONF_SPI0_D0 0x0954
#define CONTROL_PADCONF_SPI0_D1 0x0958
#define CONTROL_PADCONF_SPI0_CS0 0x095C
#define CONTROL_PADCONF_SPI0_CS1 0x0960
#define CONTROL_PADCONF_ECAP0_IN_PWM0_OUT 0x0964
#define CONTROL_PADCONF_UART0_CTSN 0x0968
#define CONTROL_PADCONF_UART0_RTSN 0x096C
#define CONTROL_PADCONF_UART0_RXD 0x0970
#define CONTROL_PADCONF_UART0_TXD 0x0974
#define CONTROL_PADCONF_UART1_CTSN 0x0978
#define CONTROL_PADCONF_UART1_RTSN 0x097C
#define CONTROL_PADCONF_UART1_RXD 0x0980
#define CONTROL_PADCONF_UART1_TXD 0x0984
#define CONTROL_PADCONF_I2C0_SDA 0x0988
#define CONTROL_PADCONF_I2C0_SCL 0x098C
#define CONTROL_PADCONF_MCASP0_ACLKX 0x0990
#define CONTROL_PADCONF_MCASP0_FSX 0x0994
#define CONTROL_PADCONF_MCASP0_AXR0 0x0998
#define CONTROL_PADCONF_MCASP0_AHCLKR 0x099C
#define CONTROL_PADCONF_MCASP0_ACLKR 0x09A0
#define CONTROL_PADCONF_MCASP0_FSR 0x09A4
#define CONTROL_PADCONF_MCASP0_AXR1 0x09A8
#define CONTROL_PADCONF_MCASP0_AHCLKX 0x09AC
#define CONTROL_PADCONF_XDMA_EVENT_INTR0 0x09B0
#define CONTROL_PADCONF_XDMA_EVENT_INTR1 0x09B4
#define CONTROL_PADCONF_WARMRSTN 0x09B8
#define CONTROL_PADCONF_EXTINTN 0x09C0
#define CONTROL_PADCONF_TMS 0x09D0
#define CONTROL_PADCONF_TDI 0x09D4
#define CONTROL_PADCONF_TDO 0x09D8
#define CONTROL_PADCONF_TCK 0x09DC
#define CONTROL_PADCONF_TRSTN 0x09E0
#define CONTROL_PADCONF_EMU0 0x09E4
#define CONTROL_PADCONF_EMU1 0x09E8
#define CONTROL_PADCONF_RTC_PWRONRSTN 0x09F8
#define CONTROL_PADCONF_PMIC_POWER_EN 0x09FC
#define CONTROL_PADCONF_EXT_WAKEUP 0x0A00
#define CONTROL_PADCONF_RTC_KALDO_ENN 0x0A04
#define CONTROL_PADCONF_USB0_DRVVBUS 0x0A1C
#define CONTROL_PADCONF_USB1_DRVVBUS 0x0A34
#define MUX_VAL(OFFSET,VALUE) writel((VALUE), CTRL_BASE + (OFFSET));
#define MUX_EVM() \
MUX_VAL(CONTROL_PADCONF_GPMC_AD0, (IEN | PD | MODE1 )) /* mmc1_dat0_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD1, (IEN | PD | MODE1 )) /* mmc1_dat1_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD2, (IEN | PD | MODE1 )) /* mmc1_dat2_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD3, (IEN | PD | MODE1 )) /* mmc1_dat3_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD4, (IEN | PD | MODE1 )) /* mmc1_dat4_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD5, (IEN | PD | MODE1 )) /* mmc1_dat5_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD6, (IEN | PD | MODE1 )) /* mmc1_dat6_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD7, (IEN | PD | MODE1 )) /* mmc1_dat7_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD8, (IDIS | PD | MODE1 )) /* lcd_data23 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD9, (IDIS | PD | MODE1 )) /* lcd_data22 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD10, (IDIS | PD | MODE1 )) /* lcd_data21 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD11, (IDIS | PD | MODE1 )) /* lcd_data20 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD12, (IDIS | PD | MODE1 )) /* lcd_data19 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD13, (IDIS | PD | MODE1 )) /* lcd_data18 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD14, (IDIS | PD | MODE1 )) /* lcd_data17 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD15, (IDIS | PD | MODE1 )) /* lcd_data16 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A0, (IEN | OFF | MODE7 )) /* gpio1[16] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | OFF | MODE7 )) /* gpio1[17] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IDIS | OFF | MODE7 )) /* gpio1[18] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | OFF | MODE7 )) /* gpio1[19] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PU | MODE7 )) /* gpio1[20] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IDIS | PD | MODE7 )) /* gpio1[21] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IDIS | PD | MODE7 )) /* gpio1[22] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IDIS | OFF | MODE7 )) /* gpio1[23] */\
MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | OFF | MODE6 )) /* mcasp0_aclkx_mux3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | OFF | MODE6 )) /* mcasp0_fsx_mux3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PD | MODE6 )) /* mcasp0_axr0_mux3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IDIS | OFF | MODE6 )) /* mcasp0_axr1_mux3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | MODE6 )) /* uart4_rxd_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_WPN, (IDIS | PU | MODE6 )) /* uart4_txd_mux2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_BEN1, (IDIS | OFF | MODE7 )) /* gpio1[28] */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN0, (IEN | OFF | MODE7 )) /* gpio1[29] */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN1, (IEN | PU | MODE2 )) /* mmc1_clk_mux0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN2, (IEN | PU | MODE2 )) /* mmc1_cmd_mux0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN3, (IEN | OFF | MODE7 )) /* gpio2[0] */\
MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IDIS | OFF | MODE7 )) /* gpio2[1] */\
MUX_VAL(CONTROL_PADCONF_GPMC_ADVN_ALE, (IDIS | OFF | MODE7 )) /* gpio2[2] */\
MUX_VAL(CONTROL_PADCONF_GPMC_OEN_REN, (IDIS | OFF | MODE7 )) /* gpio2[3] */\
MUX_VAL(CONTROL_PADCONF_GPMC_WEN, (IDIS | OFF | MODE7 )) /* gpio2[4] */\
MUX_VAL(CONTROL_PADCONF_GPMC_BEN0_CLE, (IEN | OFF | MODE7 )) /* gpio2[5] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA0, (IEN | OFF | MODE0 )) /* lcd_data0 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA1, (IEN | OFF | MODE0 )) /* lcd_data1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA2, (IEN | OFF | MODE0 )) /* lcd_data2 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA3, (IEN | OFF | MODE0 )) /* lcd_data3 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA4, (IEN | OFF | MODE0 )) /* lcd_data4 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA5, (IEN | OFF | MODE0 )) /* lcd_data5 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA6, (IEN | OFF | MODE0 )) /* lcd_data6 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA7, (IEN | OFF | MODE0 )) /* lcd_data7 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA8, (IEN | OFF | MODE0 )) /* lcd_data8 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA9, (IEN | OFF | MODE0 )) /* lcd_data9 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA10, (IEN | OFF | MODE0 )) /* lcd_data10 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA11, (IEN | OFF | MODE0 )) /* lcd_data11 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA12, (IEN | OFF | MODE0 )) /* lcd_data12 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA13, (IEN | OFF | MODE0 )) /* lcd_data13 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA14, (IEN | OFF | MODE0 )) /* lcd_data14 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA15, (IEN | OFF | MODE0 )) /* lcd_data15 */\
MUX_VAL(CONTROL_PADCONF_LCD_VSYNC, (IEN | OFF | MODE0 )) /* lcd_vsync */\
MUX_VAL(CONTROL_PADCONF_LCD_HSYNC, (IDIS | OFF | MODE0 )) /* lcd_hsync */\
MUX_VAL(CONTROL_PADCONF_LCD_PCLK, (IDIS | OFF | MODE0 )) /* lcd_pclk */\
MUX_VAL(CONTROL_PADCONF_LCD_AC_BIAS_EN, (IDIS | OFF | MODE0 )) /* lcd_ac_bias_en */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT3, (IEN | PU | MODE0 )) /* mmc0_dat3 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT2, (IEN | PU | MODE0 )) /* mmc0_dat2 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT1, (IEN | PU | MODE0 )) /* mmc0_dat1 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT0, (IEN | PU | MODE0 )) /* mmc0_dat0 */\
MUX_VAL(CONTROL_PADCONF_MMC0_CLK, (IEN | PU | MODE0 )) /* mmc0_clk */\
MUX_VAL(CONTROL_PADCONF_MMC0_CMD, (IEN | PU | MODE0 )) /* mmc0_cmd */\
MUX_VAL(CONTROL_PADCONF_MII1_COL, (IEN | OFF | MODE7 )) /* gpio3[0] */\
MUX_VAL(CONTROL_PADCONF_MII1_CRS, (IEN | OFF | MODE7 )) /* gpio3[1] */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_ER, (IDIS | OFF | MODE7 )) /* gpio3[2] */\
MUX_VAL(CONTROL_PADCONF_MII1_TX_EN, (IEN | PD | MODE2 )) /* rgmii1_tctl */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_DV, (IEN | PD | MODE2 )) /* rgmii1_rctl */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD3, (IDIS | PD | MODE2 )) /* rgmii1_td3 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD2, (IDIS | PD | MODE2 )) /* rgmii1_td2 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD1, (IEN | PD | MODE2 )) /* rgmii1_td1 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD0, (IEN | PD | MODE2 )) /* rgmii1_td0 */\
MUX_VAL(CONTROL_PADCONF_MII1_TX_CLK, (IDIS | PD | MODE2 )) /* rgmii1_tclk */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_CLK, (IEN | PD | MODE2 )) /* rgmii1_rclk */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD3, (IEN | PD | MODE2 )) /* rgmii1_rd3 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD2, (IEN | PD | MODE2 )) /* rgmii1_rd2 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD1, (IEN | PD | MODE2 )) /* rgmii1_rd1 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD0, (IEN | PD | MODE2 )) /* rgmii1_rd0 */\
MUX_VAL(CONTROL_PADCONF_RMII1_REF_CLK, (IDIS | PU | MODE5 )) /* mmc0_pow_mux0 */\
MUX_VAL(CONTROL_PADCONF_MDIO, (IEN | PU | MODE0 )) /* mdio_data */\
MUX_VAL(CONTROL_PADCONF_MDC, (IDIS | PU | MODE0 )) /* mdio_clk */\
MUX_VAL(CONTROL_PADCONF_SPI0_SCLK, (IEN | OFF | MODE7 )) /* spi0_sclk */\
MUX_VAL(CONTROL_PADCONF_SPI0_D0, (IEN | OFF | MODE7 )) /* spi0_d0 */\
MUX_VAL(CONTROL_PADCONF_SPI0_D1, (IEN | OFF | MODE7 )) /* spi0_d1 */\
MUX_VAL(CONTROL_PADCONF_SPI0_CS0, (IEN | OFF | MODE7 )) /* spi0_cs0 */\
MUX_VAL(CONTROL_PADCONF_SPI0_CS1, (IEN | OFF | MODE5 )) /* mmc0_sdcd_mux0 */\
MUX_VAL(CONTROL_PADCONF_ECAP0_IN_PWM0_OUT, (IEN | OFF | MODE7 )) /* gpio0[7] */\
MUX_VAL(CONTROL_PADCONF_UART0_CTSN, (IEN | OFF | MODE3 )) /* I2C1_SDA_mux1 */\
MUX_VAL(CONTROL_PADCONF_UART0_RTSN, (IEN | OFF | MODE3 )) /* I2C1_SCL_mux1 */\
MUX_VAL(CONTROL_PADCONF_UART0_RXD, (IEN | OFF | MODE0 )) /* uart0_rxd */\
MUX_VAL(CONTROL_PADCONF_UART0_TXD, (IDIS | OFF | MODE0 )) /* uart0_txd */\
MUX_VAL(CONTROL_PADCONF_UART1_CTSN, (IEN | OFF | MODE3 )) /* I2C2_SDA_mux0 */\
MUX_VAL(CONTROL_PADCONF_UART1_RTSN, (IEN | OFF | MODE3 )) /* I2C2_SCL_mux0 */\
MUX_VAL(CONTROL_PADCONF_UART1_RXD, (IEN | OFF | MODE0 )) /* uart1_rxd */\
MUX_VAL(CONTROL_PADCONF_UART1_TXD, (IDIS | OFF | MODE0 )) /* uart1_txd */\
MUX_VAL(CONTROL_PADCONF_I2C0_SDA, (IEN | OFF | MODE0 )) /* I2C0_SDA */\
MUX_VAL(CONTROL_PADCONF_I2C0_SCL, (IEN | OFF | MODE0 )) /* I2C0_SCL */\
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKX, (IEN | PD | MODE3 )) /* spi1_sclk_mux2 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_FSX, (IEN | PD | MODE3 )) /* spi1_d0_mux2 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR0, (IEN | PD | MODE3 )) /* spi1_d1_mux2 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKR, (IEN | PD | MODE3 )) /* spi1_cs0_mux4 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKR, (IEN | OFF | MODE7 )) /* gpio3[18] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_FSR, (IEN | OFF | MODE7 )) /* gpio3[19] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR1, (IEN | OFF | MODE7 )) /* gpio3[20] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKX, (IEN | PU | MODE7 )) /* gpio3[21] */\
MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR0, (IEN | OFF | MODE0 )) /* xdma_event_intr0 */\
MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR1, (IDIS | OFF | MODE3 )) /* clkout2 */\
MUX_VAL(CONTROL_PADCONF_WARMRSTN, (IEN | OFF | MODE0 )) /* nRESETIN_OUT */\
MUX_VAL(CONTROL_PADCONF_EXTINTN, (IEN | OFF | MODE0 )) /* nNMI */\
MUX_VAL(CONTROL_PADCONF_TMS, (IEN | PU | MODE0 )) /* TMS */\
MUX_VAL(CONTROL_PADCONF_TDI, (IEN | PU | MODE0 )) /* TDI */\
MUX_VAL(CONTROL_PADCONF_TDO, (IDIS | PU | MODE0 )) /* TDO */\
MUX_VAL(CONTROL_PADCONF_TCK, (IEN | PU | MODE0 )) /* TCK */\
MUX_VAL(CONTROL_PADCONF_TRSTN, (IEN | PD | MODE0 )) /* nTRST */\
MUX_VAL(CONTROL_PADCONF_EMU0, (IEN | PU | MODE0 )) /* EMU0 */\
MUX_VAL(CONTROL_PADCONF_EMU1, (IEN | PU | MODE0 )) /* EMU1 */\
MUX_VAL(CONTROL_PADCONF_RTC_PWRONRSTN, (IEN | OFF | MODE0 )) /* RTC_porz */\
MUX_VAL(CONTROL_PADCONF_PMIC_POWER_EN, (IDIS | PU | MODE0 )) /* PMIC_POWER_EN */\
MUX_VAL(CONTROL_PADCONF_EXT_WAKEUP, (IEN | PD | MODE0 )) /* EXT_WAKEUP */\
MUX_VAL(CONTROL_PADCONF_RTC_KALDO_ENN, (IEN | OFF | MODE0 )) /* ENZ_KALDO_1P8V */\
MUX_VAL(CONTROL_PADCONF_USB0_DRVVBUS, (IDIS | PD | MODE0 )) /* USB0_DRVVBUS */\
MUX_VAL(CONTROL_PADCONF_USB1_DRVVBUS, (IDIS | PD | MODE0 )) /* USB1_DRVVBUS */\
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux uart1_pin_mux[] = {
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
{-1},
};
static struct module_pin_mux uart2_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
{-1},
};
static struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
{-1},
};
static struct module_pin_mux uart4_pin_mux[] = {
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
{-1},
};
static struct module_pin_mux uart5_pin_mux[] = {
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
{-1},
};
static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux spi0_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
{-1},
};
static struct module_pin_mux gpio0_7_pin_mux[] = {
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
{-1},
};
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
static struct module_pin_mux bone_norcape_pin_mux[] = {
{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
{OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
{OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
{OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
{OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
{OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
{OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
{OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
{OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
{OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
{OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
{OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
{OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
{OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
{OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
{OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
{OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
{OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
{OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
{OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
{-1},
};
#endif
#if defined(CONFIG_NOR_BOOT)
void enable_norboot_pin_mux(void)
{
/*
* The ROM will only have set up sufficient pinmux to allow for the
* first 4KiB NOR to be read, we must finish doing what we know of
* the NOR mux in this space in order to continue. We do this in
* assembly to avoid having to play linker games to ensure that all
* functions and data sections are in this special area.
*/
asm("stmfd sp!, {r2 - r4}");
asm("movw r4, #0x8A4");
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9");
asm("mov r3, #8");
asm("gpmc_mux: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux");
asm("ldmfd sp!, {r2 - r4}");
}
#endif
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_uart1_pin_mux(void)
{
configure_module_pin_mux(uart1_pin_mux);
}
void enable_uart2_pin_mux(void)
{
configure_module_pin_mux(uart2_pin_mux);
}
void enable_uart3_pin_mux(void)
{
configure_module_pin_mux(uart3_pin_mux);
}
void enable_uart4_pin_mux(void)
{
configure_module_pin_mux(uart4_pin_mux);
}
void enable_uart5_pin_mux(void)
{
configure_module_pin_mux(uart5_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
/*
* The AM335x GP EVM, if daughter card(s) are connected, can have 8
* different profiles. These profiles determine what peripherals are
* valid and need pinmux to be configured.
*/
#define PROFILE_NONE 0x0
#define PROFILE_0 (1 << 0)
#define PROFILE_1 (1 << 1)
#define PROFILE_2 (1 << 2)
#define PROFILE_3 (1 << 3)
#define PROFILE_4 (1 << 4)
#define PROFILE_5 (1 << 5)
#define PROFILE_6 (1 << 6)
#define PROFILE_7 (1 << 7)
#define PROFILE_MASK 0x7
#define PROFILE_ALL 0xFF
/* CPLD registers */
#define I2C_CPLD_ADDR 0x35
#define CFG_REG 0x10
static unsigned short detect_daughter_board_profile(void)
{
unsigned short val;
if (i2c_probe(I2C_CPLD_ADDR))
return PROFILE_NONE;
if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
return PROFILE_NONE;
return (1 << (val & PROFILE_MASK));
}
void enable_board_pin_mux(struct am335x_baseboard_id *header)
{
//Addition by Matt Minga
MUX_EVM();
//#if 0
/* Do board-specific muxes. */
//if (board_is_bone(header)) {
/* Beaglebone pinmux */
//configure_module_pin_mux(i2c1_pin_mux);
//configure_module_pin_mux(mii1_pin_mux);
//configure_module_pin_mux(mmc0_pin_mux);
#ifndef CONFIG_NOR
//configure_module_pin_mux(mmc1_pin_mux);
#endif
#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
//configure_module_pin_mux(bone_norcape_pin_mux);
#endif
#if 0
//} else if (board_is_gp_evm(header)) {
/* General Purpose EVM */
// unsigned short profile = detect_daughter_board_profile();
// configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
/* In profile #2 i2c1 and spi0 conflict. */
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
/* Profiles 2 & 3 don't have NAND */
if (profile & ~(PROFILE_2 | PROFILE_3))
configure_module_pin_mux(nand_pin_mux);
else if (profile == PROFILE_2) {
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
}
} else if (board_is_idk(header)) {
/*
* Industrial Motor Control (IDK)
* note: IDK console is on UART3 by default.
* So u-boot mus be build with CONFIG_SERIAL4 and
* CONFIG_CONS_INDEX=4
*/
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_no_cd_pin_mux);
} else if (board_is_evm_sk(header)) {
/* Starter Kit EVM */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(gpio0_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
} else if (board_is_bone_lt(header)) {
/* Beaglebone LT pinmux */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
} else {
puts("Unknown board, cannot configure pinmux.");
hang();
}
#endif
}
