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[AM335x] init_priority register bit field

Naoki Kawada
Guru 19890 points

Hi,

About init_priority register. The following post (Actually, that is my post) says lowest value (0) indicates having highest priority to interconnect (and highest value (7) is lowest priority to interconnect).

http://e2e.ti.com/support/arm/sitara_arm/f/791/p/364090/1282805.aspx#1282805

But now I found the following descriptions in TRM:

===================================

9.2.4.3.1 Initiator Priority Control for Interconnect

The priority can take a value from 0 to 3. The following table gives the valid set of priority values.
Interconnect Priority Value Remarks
00                              Low priority
01                              Medium priority
10                              Reserved
11                              High priority

===================================

Which descriptions are correct ?

Best  Regards,
Kawada 

 

  • 0
    TI__Guru**** 393215 points

    Hi Kawada-san,

    From what I see your other post is about MREQPRIO registers. From TRM:

    9.2.4.3.2 Initiator Priority at EMIF

    The MREQPRIO register provides an interface to change the access priorities for the various masters accessing the EMIF(DDR). Software can make use of this register to set the requestor priorities for required EMIF arbitration. The EMIF priority can take a value from 000b to 111b where 000b will be the highest priority and 111b will be lowest priority.

    So as you see priority order is different for MREQPRIOx and INIT_PRIORITYx.

  • 0 in reply to Biser Gatchev-XID
    Guru 19890 points

    Hi Biser,

    Thanks for your quick reply. It seems I have confused the values between init_priority and mreqprio...  Now I fully understood. Sorry to bother you so much.

    Thanks,
    Kawada