Hi, I have some questions about routing two DDR2 RAM to one TMS320DM648
1) PCB Impedanz Z0 on Layer0: 68R, on Layer1: 55R.
If a route one Signal (e.g. CK) on these two Layers, could this be a problem?
2) Datasheet SPRS372E MAY 2007 Revised September 2009
Page 99 Table6-37
CK and ADDR_CTRL Routing:
The CACLM is 45,2mm but in my Layout it nearly seems to be impossible to route this specification because the Manhattan Length in the T-Cross in Figure 6-16 are straight lines und I need a little bit Trace for routing. I have a routing length for the net Class ADDR_CTRL of 49mm +-0,2mm.
3) Datasheet SPRS372E MAY 2007 Revised September 2009
Page 100 Table6-38
DQS and DQ Routing:
DQLM is 27.1 mm but I think it is possible to route this classes with 23
(Manhattan length = 27.1mm straight length = 20.0mm )
4) Could the mismatch of DQLM to CACLM be a Problem to the DDR2 Timing?
5) Datasheet SPRS372E MAY 2007 Revised September 2009
Page 98 Table6-38
Clock Net Class
DQGATEH = CK, DQS2, DQS3, DDR_DQGATE2, DDR_DQGATE3
On Page 101 DQGATEH should be CKB2B3
CKB2B3 = length CK net + average length DQS0 and DQS1 nets
I think this length rule is only for the net DQGATE23 right?
6) Are the implementation Guidelines in SPRAAG6D Revised January 2010 an update of the DDR2 Routing Specifications from the Datasheet SPRS372E MAY 2007 Revised September 2009? Exists special routing rules for DDR2 for different Controller (two embedded DDR2 with one DDR2 Controller)?
7)In the SPRAAG6D rules for vias.
Are vias limited because of Impedanz changes?
Are these limits just for PTH (plated through hole) Vias or also for Micro Vias (Laser Vias from Layer 1 to Layer3, Layer 2 ground)?
Unfortunately my PCB-CAD do not calculate Via lenght to the net length.
Is the via length includet in the maximum of allowed vias or must I calculate the via length manually to each net length?
8) The rule 1 via for each Power Connection Ball (DDR2 Controller):
I placed the TMS320 on the PCB top side and the 0402 ceramic cap on the bottom side under the TMS BGA power ball.
Now it seams to be impossible to make one via for one TMS BGA ball.
I made one via for two TMS BGA power balls and use the same Via for the HS bypass capacitor on the other side. Is this OK or is it better to place the HS bypass capacitor outside of the TMS and connect each TMS BGA power ball with one via to the power plane? I think a less distance to the capacitor is better.
Hopefully someone can answer the Questions
Dati