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McASP Frame sysnc error

Genius 5785 points


Hello,

I'll use McASP below.

- TX and RX
- TDM mode: number of slots is 3
- Slot format: 32-bit slot, available data is 10-bit, left align(beginning)
- Master: FPGA sends FS and ACLK to C672x

Sometimes the last slot has the data width of 31-bit or 33-bit (Not 32-bit). I mean the position of pad bits are elastic on the last slot. It's a specification of my system, and may be unusual.

I think it leads to occur XSYNCERR and RSYNCERR. But I'll ignore this error. It's important for me that current frame data will not be broken by SYNCERR. I also understand next frame can resync. There are four error cases, Early-RX, Early-TX, Late-RX and Late-TX. I hope each cases is that the current frame data is readable or sendable correctly, the next frame can resync. Please give me the informations.

C672x McASP RG (SPRU878B)
3.6.1 Unexpected Frame Sync Error

Regards,
Kazu

  • Any advice or information you could provide would be appreciated.

  • Hi,

    Thanks for your post.

    During the unexpected frame sync error, the current bit clock will not by synchronized but the next frame after it completes the current frame will be re-synchronized.

    Usually, the framesync should occur exactly during the correct bit clock instance, else an unexpected frame sync will happen for a current frame. In case, a new framesync is detected when the McASP is in the process of completing the current frame, then an early unexpected frame sync will occur and in the other case, when there is a delay between the the last bit of the previous frame and the first bit of the next frame, a late unexpected frame sync will occur. This would set the error interrupt flag XSYNCERR and RSYNCERR on tx. and rx for both the late and early unexpected framesync cases.

    Thanks & regards,

    Sivaraj K

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  • Hello Sivaraj,

    Thank you for your reply. I'm not sure about "current" frame. Is my understanding correct? For example, case of the early unexpected RX frame sync:
    - The last slot of previous frame which is interrupted by unexpected frame sync will send to XRSR and XRBUF correctly.
    - The current frame which is occuring unexpected frame sync will not synchronized. It means that these slots in this frame will not send to XRBUF and be lost.
    - The next frame will re-synchronized. These slots data will send to XRBUF correctly.

    Regards,
    Kazu

  • Kazu,

    Yes, exactly your understanding is perfectly fine with my intended saying.

    Thanks & regards,
    Sivaraj K

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  • Hello Sivaraj,

    Thank you for your answer. How about Late-RX? I think there are extra bits between the last slot of previous frame and the next frame sync signal. Does RSYNCERR occur at beginning of the extra bits? And is my following understanding correct?
    - The last slot of previous frame which is before extra bits will send to XRBUF correctly.
    - The extra bits will not synchronized. It means that these bits will not send to XRBUF and be lost.
    - The next frame will re-synchronized. These slots data will send to XRBUF correctly.

    Regards,
    Kazu

  • Hi,

    Thanks for your update.

    Even if it is previous frame or next frame, the McASP's transmit sync as well the receive sync can be resynchronized upt to 1 or 2-bit delay and beyond this, it will throw XSYNCERR or RSYNCERR. For extra bits on any previous frame or next frame, it should thow RSYNCERR/XSYNCERR as the data will be able to re-align or re-synchronize. Please refer the code snippets below for the adjustable bit delay:

    /* Transmit Sync Bit delay */
    #define MCASP_TX_SYNC_DELAY_0BIT             (MCASP_XFMT_XDATDLY_0BIT \
    << MCASP_XFMT_XDATDLY_SHIFT)
    
    #define MCASP_TX_SYNC_DELAY_1BIT             (MCASP_XFMT_XDATDLY_1BIT \                               
    << MCASP_XFMT_XDATDLY_SHIFT)
    
    #define MCASP_TX_SYNC_DELAY_2BIT             (MCASP_XFMT_XDATDLY_2BIT \
    << MCASP_XFMT_XDATDLY_SHIFT)
    
    * Receive Bit delay */
    #define MCASP_RX_SYNC_DELAY_0BIT             (MCASP_RFMT_RDATDLY_0BIT \
    << MCASP_RFMT_RDATDLY_SHIFT)
    
    #define MCASP_RX_SYNC_DELAY_1BIT             (MCASP_RFMT_RDATDLY_1BIT \
    << MCASP_RFMT_RDATDLY_SHIFT)
    
    #define MCASP_RX_SYNC_DELAY_2BIT             (MCASP_RFMT_RDATDLY_2BIT \
    << MCASP_RFMT_RDATDLY_SHIFT)
    
    Thanks & regards,
    Sivaraj K

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  • Hello Sivaraj,

    Thank you for your advice. But I think I can't use a capability of delay because the delay is nothing (0-bit) between frame sync signal and beginning bit of first slot. Our system in the case of Late sync error will have a chance of extra bits between frame sync signal and ending bit of last slot of previous frame. Could you tell me about previous my question or any advice?

    Regards,
    Kazu

  • Hi,

    Regarding your previous question, yes, ofcourse, an unexpected late Rx. framesync will occur (RSYNCERR) since it will introduce delay because of extra bits between the last slot of previous frame and the next frame sync signal.

    Hope, it clarifies your previous question.

    Thanks & regards,

    Sivaraj K

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