Hello,
I'll use McASP below.
- TX and RX
- TDM mode: number of slots is 3
- Slot format: 32-bit slot, available data is 10-bit, left align(beginning)
- Master: FPGA sends FS and ACLK to C672x
Sometimes the last slot has the data width of 31-bit or 33-bit (Not 32-bit). I mean the position of pad bits are elastic on the last slot. It's a specification of my system, and may be unusual.
I think it leads to occur XSYNCERR and RSYNCERR. But I'll ignore this error. It's important for me that current frame data will not be broken by SYNCERR. I also understand next frame can resync. There are four error cases, Early-RX, Early-TX, Late-RX and Late-TX. I hope each cases is that the current frame data is readable or sendable correctly, the next frame can resync. Please give me the informations.
C672x McASP RG (SPRU878B)
3.6.1 Unexpected Frame Sync Error
Regards,
Kazu