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what is the adc sampling speed of am3359?

Tao He1
Intellectual 320 points
Other Parts Discussed in Thread: AM3359

hello all,

We are planning to use the am3359 platform for some adc applications and the speed of the adc module is our main consideration.

We have checked some official materials, and it seems the sampling frequency of the adc module in am3359 is only 200K (see the following figure grabbed from one datasheet of am3359):

But in another more detailed official datasheet of am3359, we get the following information that the sampling frequency could be as fast as 15 every adc clock cycles.
So we carried on some experiment and set the adc clock cycle to 24M, and the every adc time only took 1.5 us, which is very matched to the explanation shown above, but obviously the adc frequency is not 200K as mentioned in the very beginning.
We wander what is the real adc sampling frequency of am3359. We appreciate any direction! 
Thank you!
Tao
  • 0
    TI__Guru**** 393215 points

    Hi Tao,

    If you look in the "Sampling Dynamics" section of Table 5-16 in the AM335X Datasheet, Rev. G (p.97) you will see that the 200kSPS value is for 3MHz ADC clock and that the minimum conversion time is indeed 15 ADC clock cycles. There are also 2 ADC clock cycles acquisition time to add to that, and with some SW overhead and interconnect latencies what you have measured is correct.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 320 points

    Hello Biser,

    Thank you for your explanation. So is it ok to say that the speed of ADC module in am3359 is depend on the frequency of the ADC clock? So if we want to increase the ADC sampling speed, is ok to set a fast ADC clock and what is maximum frequency of the ADC clock? 

    Thank you!

    tao

  • 0 in reply to Tao He1
    TI__Guru**** 393215 points

    The maximum ADC clock rate is 24MHz (Table 12-2 from the AM335X TRM Rev. K). Also Note 1 below the table is important:

    When using master input clock frequencies (CLK_M_OSC) above 24 MHz (that is, 25 or 26 MHz), the ADC clock must be divided down using the ADC_CLKDIV register, which will reduce the maximum potential sample rate. The maximum sample rate can only be achieved using a 24-MHz master input clock.

    Edit:

    The TRM is discussing the pre-divider clock limit of 24MHz. The post-divider limit is 3MHz. It takes 15 clock cycles per sample, minimum of two cycles for acquisition and 13 cycles for conversion.  So a 3MHz post-divider clock gives the maximum sample rate of 200kSPS.