• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 326 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6678 Design Constraints Requirement

Avinash Neethi1
Expert 2125 points

Dear All,

Our Design Engineers has completed there Placement for QUAD DSP Board. I want certain clarification before Manufacturing the board.

Due to Area Constrains our placement engineers has placed the Power Module Near the DSP & DDR3 Chip. 

Due to this there can be any issues in accessing the DDR3 through DSP.

I have attached the Image For reference.

Can any one provide there suggestions. As we re running out of time for Manufacturing.


Thanks in Advance.

Regards,

Avinash N

  • 0
    TI__Mastermind 46460 points

    Avinash,

    It depends on your power supply and power and ground plane layouts.  Noise can couple into the DDR3 circuitry if not managed properly.  Be sure to arrange the power supply components such that the large AC ripple currents (including those in the ground connections) remain isolated to the top layer.  Be sure to have adequate decoupling.  You may need to perform a Power Integrity analysis to be certain you have chosen proper capacitors and placement.  DDR3 power planes and routing must be isolated from noise sources.  That is the purpose of the keep-out guidelines.

    Tom