Hello,
when looking at the DDR3 controller SDCFG register it looks like there's an error in the documentation regarding the CWL [17:16] and the SDRAM_DRIVE [19:18] fields. The CWL field is 2 bits wide, yet values that require up to 3 bits can be written.
The error is also present in the DDR3 Register Calc v4 spreadsheet and the GEL files.
Can I assume that the CWL field should be [18:16] and SDRAM_DRIVE should be [19]?
Hello Oane,
Yes, there is an error in SDCFG.CWL field description in the Rev D document.
The CWL field in SDCFG register has only four selection of DDR3 CAS Write latency. Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved.
The field description was correct in Rev C document and the details are given below. I hope the error in Rev D will be corrected in the next revision of the document.
Regards,
Senthil
