TI-RTOS NDK two port switch mode problem

Hello,

Can you please share more details? Is the implementation based on CPSW or ICSS? Which platform?

Regards,
Vinesh

Hello Vinesh,

        Very glad to see your replay.Cause I just follow your post(http://e2e.ti.com/support/embedded/tirtos/f/355/p/268788/1351759.aspx#1351759) to implement my platform.In our platform we use CPSW driver to implement the stack porting, most of the code is copy from the ind sdk.

Our hardware is custom design board which connect two phy by RGMII way to the 3 port switch.

By the way I also have the problem of set 2 ip address to the interface 1 and 2. see my reply on your old post. Could you help to support me?

Thank you very much!

Hello,

On CPSW, we haven't seen this issue on our boards. The behavior is strange though, not sure why a link change is stabilizing the setup.

On enabling IP address for second interface, have you modified the CPSW driver to enable two instances?

Regards,
Vinesh

Hello Vinesh,

     Thanks! On hardware initial side I think it should be OK in my program. My application is to use port 1 as EtherCAT master and port 2 to HMI to some other usage. Now if I connect port 1 to ethercat slave and port 2 to my PC. I am able to get all of the ethercat message flow from PC cause the ethercat message is always boardcast message. And the ethercat slave is running OK in my last 24 hour test.

So I think the driver are all config currectly. The Problem may be in side some of the os layer driver between NDK and CPSW.

    From your post in http://e2e.ti.com/support/embedded/tirtos/f/355/p/268788/1351759.aspx#1351759, you was also met with random ping timeout, and you said finally you currect it by change something in driver. Could you be able to recall which should be change in driver?

One more thing is how to enable two instance in NDK? My initial config is like:

MAC_CONFIG config;

Eth_HW_Init();

config.phyAddr[0] = PHY_ADDRESS_Port0;
config.phyAddr[1] = PHY_ADDRESS_Port1;
config.numberPorts = 2;
config.macModeFlags = CPSW_CONFIG_MODEFLG_GIGABIT| CPSW_CONFIG_MODEFLG_FULLDUPLEX|CPSW_CONFIG_MODEFLG_PASSALL;
config.resvd = 1;

SetMacConfiguration(&config);

if(AddNetifEntryFn(CPSW_NETIF_INIT) == 0)
BIOS_exit(0);

Is this enough?

Thank you again!

Bin Hu1 said:

From your post in http://e2e.ti.com/support/embedded/tirtos/f/355/p/268788/1351759.aspx#1351759, you was also met with random ping timeout, and you said finally you currect it by change something in driver. Could you be able to recall which should be change in driver?

I'll have to check on what this change was.

Bin Hu1 said:

Is this enough?

No! The NDK driver provided in ISDK does NOT support Dual MAC. 

Regards,
Vinesh

Hello Vinesh,

     Thank you for your help!

By the way , cause the dual mac mode should change such a lot codes and I think the switch mode is also OK for my application. So if I just want to use as switch, how should I config the parameters I list upside?

Hello,

I thought you mentioned the switching is working fine for ECAT broadcast packets? Or are you using both ICSS and CPSW?

Regards,
Vinesh

Hello Vinesh,

Now we use the CPSW only, not use ICSS now.

Now when I connect port 1 to ethercat slave module from 3rd party and port 2 to PC, then power on the board. The am335x can control the ethercat slave module and all of the message between am335x and ecat slave node is also passed to PC through the 3 port switch inside am335x I think. Casue from PC I can see all of the ethercat packages out and in from port1. Thats why I thought the switch configuration should be OK.

Am I right?

Hello Vinesh,

I checked my code and I think should already set this MMU config, MY config is like this in my MMU_ENTRY

SYS_MMU_ENTRY applMmuEntries[] = {
{(void*)0x81000000,SYS_MMU_CACHEABLE}, //DDR - Non bufferable| Cacheable
{(void*)0x48300000,0}, //PWM - Non bufferable| Non Cacheable
{(void*)0x48200000,0}, //INTCPS,MPUSS - Non bufferable| Non Cacheable
{(void*)0x48100000,0}, //I2C2,McSPI1,UART3,UART4,UART5, GPIO2,GPIO3,MMC1 - Non bufferable| Non Cacheable
{(void*)0x48000000,0}, //UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 -Non bufferable| Non Cacheable
{(void*)0x44E00000,0}, //Clock Module, PRM, GPIO0, UART0, I2C0, - Non bufferable| Non Cacheable
{(void*)0x4A300000,0}, //PRUSS1 - Non bufferable| Non Cacheable
{(void*)0x4A100000,0}, //CPSW - Non bufferable| Non Cacheable
{(void*)0xFFFFFFFF,0xFFFFFFFF}
};

And the initial code is from SYSBIOS SDK:

int MMUInit(SYS_MMU_ENTRY mmuEntries[])
{
unsigned short itr = 0;
Mmu_FirstLevelDescAttrs attrs;

if(NULL == mmuEntries)
return -1;

Mmu_disable();

Mmu_initDescAttrs(&attrs);

attrs.type = Mmu_FirstLevelDesc_SECTION;
attrs.domain = 0;
attrs.imp = 1;
attrs.accPerm = 3;

for(itr = 0 ; mmuEntries[itr].address != (void*)0xFFFFFFFF ; itr++)
{
attrs.bufferable = ((mmuEntries[itr].attributes) & SYS_MMU_BUFFERABLE) && 1 ;
attrs.cacheable = ((mmuEntries[itr].attributes) & SYS_MMU_CACHEABLE) && 1;
#if (ti_sysbios_family_arm_a8_Mmu___VERS >= 160)
if (!attrs.bufferable && !attrs.cacheable)
attrs.tex = 0; //tex is initialized to 1 and need this to force strongly ordered
#endif
attrs.shareable = ((mmuEntries[itr].attributes) & SYS_MMU_SHAREABLE) && 1;
attrs.noexecute = ((mmuEntries[itr].attributes) & SYS_MMU_NO_EXECUTE) && 1;
Mmu_setFirstLevelDesc((Ptr)(mmuEntries[itr].address), (Ptr)(mmuEntries[itr].address) , &attrs); // PWM
}
Mmu_enable();
return 0;
}

The attrs.tex is set to 0 cause my ti_sysbios_family_arm_a8_Mmu___VERS >= 160 is true, will it cause the problem?