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6446 VPBE slave mode

Marcel5247
Prodigy 30 points

Hi

I want to operate the VPBE in slave mode with external clocking. The clocks and synchronization come from a FPGA.

After changing the registers of VPBE what I see on the logic is VSYNC and HSYNC are correct; output clock is ok; LCD_OE ok. The only problem is with the data that is not correct. I send to output a fix pattern but receive different data, also which change from frame to frame.

The most strange is that after I close the application, the data is changing from frame to frame.

Anyone has some idea? There is somebody using VPBE digital output in slave mode?

I will appreciate your help.

 

Best regards

Marcel

  • 0
    TI__Genius 14405 points

    Hi,

    I'd first make sure that the setup & hold time of the clock and sync signals that the FPGA outputs conforms to the timing spec. Please review our datasheet.

    Could you please also provide frame & blanking size and clock rate as well?   

  • 0 in reply to Paul.Yin
    TI__Genius 9775 points

    Typically the clock polarity can play a role here.  Make sure you're using the proper polarity on both the FPGA and the DaVinci device.  Are the received frames the expected size?

  • 0 in reply to Ivan Garcia
    Prodigy 30 points

    HSYNC/VSYNC are perfectly aligned to rising edge of VCLK. Jitter is no more than 200ps. Please find attached Logic Analyzer screenshots.

    VCLK rate at the moment is 12.5MHz, frame size is 720x576, positive polarity.Received frames are at expected size.

     

     

    Best regards

    Marcel

     

  • 0 in reply to Marcel5247
    TI__Genius 9775 points

    When they claim the data changes from frame to frame, can we guarantee that the neither the address pointer nor the DDR contents are changing?  Is there a way to halt the processor completely to guarantee we’re not changing any VPBE addresses or memory contents?

     

    If the processor is completely halted, the data should not be changing.

     

    You can also try to slow down the clock and see if there's a change in behavior.  This could check for ac timing issues as well as throughput issues.