Gpmc to Fpga communication (Dm8168)

Narthan Murthy

Dear all,

Processor Dm8168 2.1version.

Fpga is connected to Gpmc with CS1.
Configuration of Chip Select One (CS1)
1:Async Mode
2:Non Multiplexed address and data 16 bit.
3:Wait0

The below following link we refered:
http://e2e.ti.com/support/omap/f/849/t/306389.aspx

for example
#define GPMC_BASE_ADDR 0x50000000 -------->Gpmc Base Address
#define GPMC_FPGA_CS1_CONFIG_REG1       (0x00000060 + (0x00000030 * 1)) ------->Chip Select1 Configuration one register Base address
#define CS_SIZE_16M 0xF
---------------------------------------------------------------------------------------------------------------------------------------
please verify the below Base address calculation for fpga access is correct or not
fpga register offset is 0x00
                                      0x04
                          0x08
gpmc_to_fpga_base_addr = ioremap((GPMC_BASE_ADDR + GPMC_FPGA_CS1_CONFIG_REG1 + CS_SIZE_16M), 0x8);
--------------------------------------------------------------------------------------------------------------------------------------

1:How to Calculate the base address for CS1 to access Fpga?
2:Can we access Fpga with out using Dma?
3:what is the difference in access of fpga using dma and without using dma?

do we have any sample code to access fpga is simple way?

Thanks,
Narthan S

over 10 years ago

0 Margarita Gashova over 10 years ago

TI__Guru* 80190 points

Hello,

What is the software release that you are using here?

Best Regards,

Margarita

0 Narthan Murthy over 10 years ago in reply to Margarita Gashova

Prodigy 190 points

Dear Margarita,

Software Release details are:

ti-ezsdk_dm816x-evm_5_05_02_00
linux-2.6.37-psp04.04.00.01
u-boot-2010.06-psp04.04.00.01

Please let me now, if any more information required.

---------------------------------------------------------------------------------------------------------------------------

I found Additional points from the forum, please review and suggest you inputs

#define SZ_16M 0x01000000

unsigned long cs_1membase:

GPMC_BASE_ADDR = 0x50000000

GPMC_FPGA_CS1_CONFIG_REG1 = (0x00000060 + (0x00000030 * 1))

cs_1membase = GPMC_BASE_ADDR + GPMC_FPGA_CS1_CONFIG_REG1

we need to use the below API to get the base address

gpmc_cs_request(GPMC_CS, SZ_16M, (unsigned long *)&cs_1membase)

gpmc_to_fpga_base_addr = ioremap((cs_1membase,SZ_16M));
------------------------------------------------------------------------------------------------------------------------------------------------

Thanks,
Narthan S

0 Margarita Gashova over 10 years ago in reply to Narthan Murthy

TI__Guru* 80190 points

Hello Narthan,

I will notify our expert for help.

Best Regards,

Margarita

0 Pavel Botev over 10 years ago in reply to Narthan Murthy

TI__Guru**** 170625 points

Narthan,

See if the below pointers will be in help:

http://processors.wiki.ti.com/index.php/Common_Issue_Resulting_in_Slow_External_Memory_Performance

http://e2e.ti.com/support/embedded/linux/f/354/t/122942.aspx

http://e2e.ti.com/support/embedded/linux/f/354/t/108876.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/319801.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/322771.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/331767.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/231946.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/362707.aspx

BR
Pavel

0 Narthan Murthy over 10 years ago in reply to Pavel Botev

Prodigy 190 points

Hi Pavel,

Thanks for that e2e thread. That speaks about GPMC address mapping, which helped me to understand Chip select configuration related concepts.

Software Release details are:
ti-ezsdk_dm816x-evm_5_05_02_00
linux-2.6.37-psp04.04.00.01
u-boot-2010.06-psp04.04.00.01

GPMC Chip Select Connections:
1:CS-0 ---------> Nand Flash.
2:CS-1 ---------> Fpga(Xilinx Spartan-6)


Issue: If we do read/write operation on the address returned by standard GPMC api (such as: gpmc_cs_request) for chip select-1 leds to the below mention error.
                       "Unhandled fault: Precise External Abort on non-linefetch (0x1008) at 0xd70fe000"

Please find the details of CS-1 Related register configuration
---------------------------------------------------------------
#define GPMC_To_FPGA_CS1_CONFIG1     0x01802000
-->GPMC_FCLK_DIVIDER ====> GPMC_CLK = GPMC_FCLK
-->MUX_DATA =============> Non multiplexed mode
-->DEVICE TYPE===========> Asynchronous Mode (FPGA Device)
-->DEVICE SIZE===========> 16 bit
-->READ/WRITE TYPE=======> Asynchronous
-->READ/WRITE MULTIPLE===> Single access

#define GPMC_To_FPGA_CS1_CONFIG2     0x00070B02

#define GPMC_To_FPGA_CS1_CONFIG3     0x00020201

#define GPMC_To_FPGA_CS1_CONFIG4     0x06020b03

#define GPMC_To_FPGA_CS1_CONFIG5     0x000A070C

#define GPMC_To_FPGA_CS1_CONFIG6     0x0A000180

#define GPMC_To_FPGA_CS1_CONFIG7     0x00000F49
-->BASE ADDRESS =========> 0x9 is the base address fo CS1.(For CS0 the Base address is 0x8)
-->CSVALID ==============> is configured as per the procedure mention in the TRM.
-->MASK ADDRESS =========> Chip Select Size is 16 MB
-----------------------------------------------------------------

Below are some doubts, we have related to the current scenario:

#define GPMC_NAND_CS0_CONFIG_REG1       (0x00000060 + (0x00000030 * 0))--->Is this is the base address for CS0 ?
#define GPMC_FPGA_CS1_CONFIG_REG1       (0x00000060 + (0x00000030 * 1))--->Is this is the base address for CS1 ?

1:Do we have any procedure to calculate the Base address of Chip Selects ?
The below api's we are using to get the base address.
    if(gpmc_cs_request(cs_select_no, SZ_16M, (unsigned long *)&gpmc_base_cs1) < 0)
    {
       printk(KERN_ERR "Failed request for GPMC mem for usrp_e\n");
       return -1;
    }
    printk("Got CS1, address = %lx\n",gpmc_base_cs1);

--------Out Put--------------------
    Got CS1-Base address = 0x01000000;
-----------------------------------
2: Currently "gpmc_base_cs1" is initilize to Zero before passing to the gpmc_cs_request() api. is it correct ?

If you need any other information, please let us know........

Thanks,
Narthan S

0 Pavel Botev over 10 years ago in reply to Narthan Murthy

TI__Guru**** 170625 points

Hi Narthan,

Narthan Murthy said:
Software Release details are:
ti-ezsdk_dm816x-evm_5_05_02_00
linux-2.6.37-psp04.04.00.01
u-boot-2010.06-psp04.04.00.01

I would suggest you to try also with the latest version of u-boot and linux kernel (PSP04.04.00.02 plus several patches):

u-boot: http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

linux kernel: http://arago-project.org/git/projects/?p=linux-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

Narthan Murthy said:
#define GPMC_NAND_CS0_CONFIG_REG1 (0x00000060 + (0x00000030 * 0))--->Is this is the base address for CS0 ?

Narthan Murthy said:
#define GPMC_FPGA_CS1_CONFIG_REG1 (0x00000060 + (0x00000030 * 1))--->Is this is the base address for CS1 ?

No, it is not. See DM816x datasheet. The GPMC has two addr ranges:

1) GPMC memory - from 0x01000000 to 0x1FFFFFFF

2) GPMC registers - from 0x50000000 to 0x50FFFFFF

GPMC_CONFIG1_0 - GPMC_CONFIG1_5 : 0x50000060 + (0x00000030 * i)

GPMC_CONFIG1_0 (GPMC_NAND_CS0_CONFIG_REG1) is at 0x50000060.

GPMC_CONFIG1_1 (GPMC_FPGA_CS1_CONFIG_REG1) is at 0x50000090.

GPMC_CONFIG1_2 is at 0x500000C0.

GPMC_CONFIG1_3 is at 0x500000F0.

GPMC_CONFIG1_4 is at 0x50000120.

GPMC_CONFIG1_5 is at 0x50000150.

GPMC_CONFIG2_0 - GPMC_CONFIG2_5 : 0x50000064 + (0x00000030 * i)

GPMC_CONFIG2_0 is at 0x50000064.

GPMC_CONFIG2_1 is at 0x50000094.

GPMC_CONFIG2_2 is at 0x500000C4.

GPMC_CONFIG2_3 is at 0x500000F4.

GPMC_CONFIG2_4 is at 0x50000124.

GPMC_CONFIG2_5 is at 0x50000154.

BR
Pavel

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Gpmc to Fpga communication (Dm8168)