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[OMAP3530] THS8200 Register settings for VESA output

BH4636
Prodigy 140 points

Other Parts Discussed in Thread: THS8200, OMAP3530

We are trying to interface a THS8200 with an OMAP3530 in order to output a SVGA signal 800x600 @ 60 Hz.  Does anyone have an register settings examples for the THS8200?

  • 0
    TI__Mastermind 43875 points

    From an OMAP perspective please have a look at the following Wiki article...

    http://wiki.omap.com/index.php/Display_Subsystem

    Particularly, look at the "Adding new DVI resolutions" section.

    You may also be interested in looking at the THS8134/35 if you are only concerned with VESA video signals and not CEA video. the THS8134/35 do not require any device specific configuration, whereas the THS8200 requires additional I2C configuration in addition to the OMAP configuration.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    TI__Genius 16810 points

    Regarding THS8200 settings for the SVGA 60Hz format, VESA DE mode of operation is relevant when a processor does not output black levels during blanking. See the THS8200 settings below for the SVGA 60Hz format.  DE mode is enabled in I2C REG 0x82. 

    BR,

    LArry

    //"THS8200_800x600x60Hz-37.9khz - 40MHz DE Blanking Enabled HS/VS+/+"

    //THS8200
    //////////////////////////////////////////
    //THS8200
    //DE operation enabled in REG 0x82
    //Connect DE signal to FID pin 47 when DE operation is enabled.
    //Connect  FID pin 47 to logic low when DE opeation is disabled.
    //////////////////////////////////////////

    REG 0x03 = 0xC1 // chip_ctl           
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1        
    REG 0x1E = 0x00 // dtg_y_sync2        
    REG 0x1F = 0x00 // dtg_y_sync3        
    REG 0x20 = 0x00 // dtg_cbcr_sync1     
    REG 0x21 = 0x00 // dtg_cbcr_sync2     
    REG 0x22 = 0x00 // dtg_cbcr_sync3     
    REG 0x23 = 0x00 // dtg_y_sync_upper   
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper
           
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input       
    REG 0x34 = 0x04 // dtg_total_pixel_msb 1056 pixels per line
    REG 0x35 = 0x20 // dtg_total_pixel_lsb
    REG 0x36 = 0x80 // dtg_linecnt_msb    
    REG 0x37 = 0x01 // dtg_linecnt_lsb    
    REG 0x38 = 0x87 // dtg_mode      VESA slave     
    REG 0x39 = 0x22 // dtg_frame_field_msb 628 line per frame/field
    REG 0x3A = 0x74 // dtg_frame_size_lsb 
    REG 0x3B = 0x74 // dtg_field_size_lsb 
    REG 0x4A = 0x8C // csm_mult_gy_msb    
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb    
    REG 0x4D = 0x00 // csm_mult_bcb_lsb   
    REG 0x4E = 0x00 // csm_mult_rcr_lsb   
    REG 0x4F = 0xC0 // csm_mode           
    REG 0x70 = 0x80 // dtg_hlength_lsb   HSOUT = 128 pixels 
    REG 0x71 = 0x00 // dtg_hdly_msb       
    REG 0x72 = 0x01 // dtg_hdly_lsb       
    REG 0x73 = 0x05 // dtg_vlength_lsb  VSOUT=4 lines ( use 1 more than desired width)  
    REG 0x74 = 0x00 // dtg_vdly_msb       
    REG 0x75 = 0x01 // dtg_vdly_lsb       
    REG 0x76 = 0x00 // dtg_vlength2_lsb   
    REG 0x77 = 0x07 // dtg_vdly2_msb      
    REG 0x78 = 0xFF // dtg_vdly2_lsb      
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb  
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb  
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb  
    REG 0x82 = 0xDB // pol_cntl  HSync/VSync polarities, DE enabled in VESA mode, set to 0x5B  to disable DE operation      

    END_DATASET

  • 0 in reply to Larry Taylor
    TI__Genius 16810 points

    We will provide the addtional settings as soon as possible.