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dm8148 ddr3 sw leveling issue

Xiaoyao Li1
Prodigy 30 points

My DM8148 board has two MT41J128M16-125 DDR3 chips, use  DDR Controller 0 interface.

/*Program the DMM to Access EMIF0 and EMIF1*/
WR_MEM_32(DMM_LISA_MAP__0, 0x0);
WR_MEM_32(DMM_LISA_MAP__1, 0x0);
WR_MEM_32(DMM_LISA_MAP__2, 0x0);
WR_MEM_32(DMM_LISA_MAP__3, 0x80500100);

Timings configuration :

//DDR3 400 MHz - CL=6,CWL=5
#define DDR3_EMIF_TIM1_DEFINE_400 0x0AAAD4DB
#define DDR3_EMIF_TIM2_DEFINE_400 0x20437FDA
#define DDR3_EMIF_TIM3_DEFINE_400 0x507F83FF
#define DDR3_EMIF_REF_CTRL_DEFINE2_400 0x00000C30
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_400   0x638412B2
#define DDR3_EMIF_DDRPHYCR_DEFINE_400 0x00170209

 

The RatioSeed_TI814x.xls configuration as follows:

The results obtained after running DDR3_SlaveRatio_ByteWiseSearch_TI814x.out:

BYTE2 and BYTE0 are always zero, can not converge

2275.400MHz_DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.0.xlsx

5700.MT41J128M16.pdf

 

  • 0
    TI__Guru**** 170625 points

    Hello,

    Xiaoyao Li1 said:

    My DM8148 board has two MT41J128M16-125 DDR3 chips, use  DDR Controller 0 interface.

    /*Program the DMM to Access EMIF0 and EMIF1*/
    WR_MEM_32(DMM_LISA_MAP__0, 0x0);
    WR_MEM_32(DMM_LISA_MAP__1, 0x0);
    WR_MEM_32(DMM_LISA_MAP__2, 0x0);
    WR_MEM_32(DMM_LISA_MAP__3, 0x80500100);

    Make sure you are aligned with the below u-boot patch:

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot#FAQ

    From what I understand you are doing Byte wise software leveling on 16-bit DDR3, is that the case?

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot#ReadMe_First

    SW leveling can be done in two methods

    • Byte wise SW leveling (For 32 bit DDR interface only)

    Data macro for each byte lane is leveled independently. The Slave ratio search program will calculate optimal values for each byte lane.

    • Word wise SW leveling (For 32 bit or 16 bit DDR interface)

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling

    BR
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 30 points

    Hi,

    Is the configuration correct ?. I only use use  DDR Controller 0 interface(EMIF0) , tow 16-Bit  DDR3 chips=32-Bit total.

    Please verify the above setting and suggest if anything needs to be changed.

  • 0 in reply to Xiaoyao Li1
    TI__Guru**** 170625 points

    Hi Xiaoyao,

    Yes, your DMM_LISA_MAP settings are correct for single EMIF (DDR3_0), 512MB configuration. The patch that I provided to you in my previous post is for 1GB DDR3 single EMIF (DDR3_0).

    Xiaoyao Li1 said:
    Please verify the above setting and suggest if anything needs to be changed.

    I would recommend you to use the word wise SW leveling, as you have 16-bit DDR3 chips. Make sure you are also aligned with DM814x datasheet, section 8.13.4.2 DDR3 Routing Specifications

    BR
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 30 points

    Hi,Pavel

    Pavel Botev said:
    Make sure you are also aligned with DM814x datasheet, section 8.13.4.2 DDR3 Routing Specifications

    You mean it may be my PCB laout problem?

  • 0 in reply to Xiaoyao Li1
    TI__Guru**** 170625 points

    See also the below e2e threads (where the same DDR3 chip is used):

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/141133.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/373949.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/180437.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/120664.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/281707.aspx

    BR
    Pavel