HI ,
I am developing C6678 software. My environment is
CCS 5.4
XDC 3.5
BIOS 6.35
I want to setup the external DDR3 interface is cachable. So In my project cfg file.
I add the following command.
(1)
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.setMarMeta(0x80000000, 0x20000000, Cache.PC | Cache.PFX );
After rebooting my board ,I dump the MAR register find that MAR12 is not changed:
md.l is a shell command in my software.
RFDSP->md.l 0x01848200 0x100
01848200: 00000000 00000000 00000000 00000000 ................
01848210: 00000000 00000000 00000000 00000000 ................
01848220: 00000000 00000000 00000000 00000000 ................
01848230: 00000000 00000000 00000000 00000000 ................
01848240: 0000000d 0000000d 0000000d 0000000d ................
01848250: 0000000d 0000000d 0000000d 0000000d ................
01848260: 0000000d 0000000d 0000000d 0000000d ................
01848270: 0000000d 0000000d 0000000d 0000000c ................
Then I use my shell commmand to write he MAR register again.
mw.l 0x01848200 0x0000000f and dump the mar128 again , It shows that the register value has been changed corectly.
It means that MAR128 is writable.
I checked the funciton implement, it seems that the paramter is the MAR register address ,not DDR3 memory address ,is it right ?
function setMarMeta(baseAddr, byteSize, value)
{
var maxAddr;
var firstMar, lastMar;
var marNum;
/* caculate the maximum address */
maxAddr = baseAddr + byteSize - 1;
/* range of MAR's that need to be modified */
firstMar = baseAddr >>> 24;
lastMar = maxAddr >>> 24;
/* loop through the number of MAR registers affecting the address range */
for (marNum = firstMar; marNum <= lastMar; marNum++) {
/* set the MAR registers to the specified value */
Cache.marvalues[marNum] = value;
}
}
(2) Then I tried another method :
Cache.MAR128_159=0x0000000f;
the resust is the same as (1).
My quesiton is why (1)&(2) XDC scripit cannot setup the corresponding MAR registers?
thank you
