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OMAP4: vmmc dip in Kernel

shajin A S
Prodigy 150 points
Other Parts Discussed in Thread: TWL6030, CSD

Hi,

I'm working on a custom OMAP4460 + twl6030 platform which follows
http://omappedia.org/wiki/4AI.1.4_OMAP4_Icecream_Sandwich_Release_Notes.

In the custom board the MMC1 is operating in 4-BIT mode.
The remaining four bits (upper nibble sdmmc1_dat4 - sdmmc1_dat7) are configured as GPIO's.

On Kernel Bootup i'm seeing a vmmc voltage dip (VDDS_SDMMC1) from PMIC.
At the same instance corresponding sdmmc1 gpio's is going low.

For Example :- GPIO_108(sdmmc1_dat6) configured as GPIO output and driven High in U-Boot and Kernel.
During the vmmc dip this pin goes low. i believe this is due to vmmc cut-off.

I was wondering if this can be avoided.

Regards
Shajin

  • 0
    TI__Mastermind 29520 points

    Hello Shajin,

    Did you set 4-bit mode in your MMC driver drivers/mmc/host/omap_hsmmc.c?

    Please apply following values in the registers:

    MMCi.MMCHS_CON[5] DW8 = 0x0 - 1-bit or 4-bit Data width (DAT[0] used, MMC, SD cards)
    MMCi.MMCHS_HCTL[1] DTW = 0x1 - 0x1: 4-bit Data width (DAT[3:0] used)

    For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and
    extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and
    EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6).
    This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[5] DW8 set to1 ),
    For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value
    written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified
    for the supported bus width by the SD card.

    Is there omap_hsmmc_set_bus_width function in omap_hsmmc.c?

    static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
    {
        struct mmc_ios *ios = &host->mmc->ios;
        u32 con;

        con = OMAP_HSMMC_READ(host->base, CON);
        /* configure in DDR mode */
        if (ios->timing == MMC_TIMING_UHS_DDR50)
            con |= DDR;
        else
            con &= ~DDR;
        switch (ios->bus_width) {
        case MMC_BUS_WIDTH_8:
            OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
            break;
        case MMC_BUS_WIDTH_4:
            OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
            OMAP_HSMMC_WRITE(host->base, HCTL,
                OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
            break;
        case MMC_BUS_WIDTH_1:
            OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
            OMAP_HSMMC_WRITE(host->base, HCTL,
                OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
            break;
        }
    }

    After applying this setting you must configure unused MMC1 pads as GPIOs as change their muxmode in PAD registers:

    CONTROL_CORE_PAD0_SDMMC1_DAT3_PAD1_SDMMC1_DAT4[18:16] SDMMC1_DAT4_MUXMODE - 0x3: Select gpio_106

    CONTROL_CORE_PAD0_SDMMC1_DAT5_PAD1_SDMMC1_DAT5[2:0] SDMMC1_DAT5_MUXMODE - 0x3: Select gpio_107

    CONTROL_CORE_PAD0_SDMMC1_DAT5_PAD1_SDMMC1_DAT6[18:16] SDMMC1_DAT6_MUXMODE - 0x3: Select gpio_108

    CONTROL_CORE_PAD0_SDMMC1_DAT7_PAD1_ABE_MCBSP2_CLKX[2:0] SDMMC1_DAT7_MUXMODE - 0x3: Select gpio_109


    Best regards,

    Yanko