Keystone2 SYSCLKs

Hello H.U,

Q1. What is the SYSCLK1 frequency at above power sequence?
　　If input Clock source (SYSCLK N/P) is 100Mhz, is SYSCLK1 100Mhz?

The SYSCLK1 is the corepac operating frequency that is based on the PLL multiplier and divider settings. Please refer figure 10.7 in device data manual for more details. The SYSCLK1 might not be equal to SYSCLK P/N at all times, however it may be equal when the PLL is in bypass mode.

Q2. Is it means that c66x DSP Core Pacs frequency is SYSCLK1/1?
       Please tell me what means "/2, /3, /4" has been described in the above table.

Yes, the corepac operating frequency is SYSCLK1/1, whereas the internal dividers /2, /3, /4 are used to provide divide by clocks to various internal logics within the corepac.

Q3. I think that Internal Clock Diveiders and Shared Local Clock Divider that described in Table 10-13 can
not be changed by user.
    For example, Boot Config Module is always running at SYSCLK1/6.
　　My thinking is correct?

Yes, the internal clock dividers and shared local clock divider values are fixed and cannot be changed by the user.

Regards,

Senthil

Hello H.U,

However, I think that PLL is not set at timing of ITEM7 in Figure 10-2.
Because, Configuration Inputs pin was not latched.
So, Is SYSCLK1 equal to SYSCLK P/N isn't it?
Is the PLL in bypass mode when the device is in ITEM7 of power sequence?

During power on sequence, the PLL is in bypass mode and the SYSCLK1 is equal to SYSCLK P/N. The PLL will be switched to PLL mode during PLL intialization.

Regards,
Senthil