NAND booting on Am335x issue

Hi Elvis,

Have you tried with SYSBOOT9 set to 0?

Hi Biser,

The CONTROL_STATUS = 0x00410313, so the CONTROL_STATUS[17] = SYSBOOT[9] has been set to 0, Is my understanding right?

Regards,

Elvis

Sorry, my mistake counting the bits. Yes, it is 0. Another question - does your MLO include a header, as described in section 26.1.9 of the AM335X TRM Rev.K?

Hi Biser,

The GP header has been included as the same MLO can boot via SD card( MMC0 device ) properly.

Either NAND and MMC are non-XIP devices, which boot with the GP header, is that right?

GP header:

0000h: 0x000148b5 --> size

0004h: 0x402f0400 --> destination

Elvis

OK, that's correct. The only other thing that comes to mind is a mismatch between the ECC with which your MLO is written and the ECC that ROM code uses. Quoting from an internal discussion:

"Based on the number of spare bytes per page, the ROM boot loader will try to use the largest ECC algorithm that it can.

So for NAND flash memories with 64 bytes per page, the ROM boot loader will assume BCH8 as the ECC algorithm, which is what we have been using with all of our software, and why the ROM boot loader boots correctly from our NAND flash devices with 64 spare bytes per page.

However, when we have 112 spare bytes per page, the ROM boot loader assumes that the ECC algorithm should be BCH16.  Since we are using BCH8 during the flashing process, the ECC data in the spare memory is thus incorrect, and this is why the ROM boot loader is failing to boot."

Hi Biser,

The NAND has been used, is the 64 spare bytes flash that should be no BCH16 ECC algorithm issue, is that right?

Device ID : 0xca

Manufacture ID : 0x2c

[CortxA8] Page Size : 2048 Bytes

[CortxA8] Spare Size : 64 Bytes

[CortxA8] Pages_Per_Block : 64

[CortxA8] Number_of_Blocks : 2048

[CortxA8] Device_width : 2 Byte

[CortxA8] DeviceSize : 256 MB

Regards,

Elvis

Yes, this should default to BCH8.