AM335x L1P/L1D

g.f.

Hi,

I have questions about AM335x.

There are SED(Single error detection) in L1D/L1P.
Does this SED support error detection and also bit error correction?
If it is supporting the bit error correction,
can user confirm that the bit error was corrected or not?

best regards,
g.f.

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Hi g.f,

ARM Cortex-A8 documentation can be found on the ARM site: http://arm.com/

0 g.f. over 11 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Hi Biser,

Thank you for the reply.

I already check the Cortex-A8 Technical Reference manual which is released from ARM.com .
But I can't find the word "SED" or "single error detection".
There are "Cache parity error detection" for instruction cache and data cache.
Is this same meaning for SED?

If yes, it seems that "Cache parity error detection" only detect the error but
it never correct the error. Is it correct?

best regards,
g.f.

0 Brad Griffis over 11 years ago in reply to g.f.

TI__Guru*** 125430 points

g.f. said:
If yes, it seems that "Cache parity error detection" only detect the error but
it never correct the error. Is it correct?

Yes, you can detect but not correct.

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AM335x L1P/L1D