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SPI NOR booting issue in am335x

Ankur Tank
Expert 2985 points

Hi ,

We are using BBB(am335x) based custom board.
Boot device for board is SPI NOR flash i.e. SPL resides in the SPI NOR flash.
We had created four partitions in the SPI NOR flash (128k bytes each) and we were expecting that if first partition doesn't contain the valid SPL copy then ROM code would try next partition as it does for NAND Flash.

But during experiment we found that ROM code actually doesn't go to next partition.

While referring TRM of AM335x we found that ROM Code checks 4 sectors(1 sector = 512 bytes) for valid SPL.
(TRM section : 26.1.7.6.3 SPI Read Sector Procedure).
BUt another section of the TRM says for SPI NOr also ROM code checks 4 blocks.
(TRM section : 26.1.7.7 Blocks and Sectors Search Summary).

Now i have following question regarding this.
1. If ROM code checks 4 blocks for SPI NOR flash, what is the size of the block. Is block size equal to sector size(512 bytes)
2. Is there any way to maintain multiple copies of SPL in SPI NOR and ROM code goes checking all the copies of SPL in SPI NOR before going to Next device?


Thank you,

Regards,
Ankur

  • 0
    TI__Guru**** 393215 points

    Hi Ankur,

    Ankur Tank said:
    1. If ROM code checks 4 blocks for SPI NOR flash, what is the size of the block. Is block size equal to sector size(512 bytes)

    Yes, this is correct.

    Ankur Tank said:
    2. Is there any way to maintain multiple copies of SPL in SPI NOR and ROM code goes checking all the copies of SPL in SPI NOR before going to Next device?

    The ROM code will stop checking when it finds the first occurrence of SPL as described in section 26.1.7.6.3 of the TRM.

  • 0 in reply to Biser Gatchev-XID
    Expert 2985 points

    Hi Biser,

    Thank you for reply,

    Does ROM code validates SPL binary ?(checksum or something )
    and if checksum fails, doesn't it try another partition/block/sector ?

    Thank you,

    Regards,
    Ankur

  • 0 in reply to Ankur Tank
    TI__Guru**** 393215 points

    No, as stated in TRM section 26.1.7.6.3:

    The ROM Code reads SPI data from the boot device in 512 byte sectors. For each call to the SPI Read Sector routine, the SPI Read Command (0x03) is sent along with the 24 bit start address of the data to be read. Each Sector = 512bytes and the ROM bootloader will attempt the following:
    1. Read Sector 1, Check the address: 0x0
    2. Read Sector 2, Check the address: 0x200
    3. Read Sector 3, Check the address: 0x400
    4. Read Sector 4, Check the address: 0x600
    The addresses mentioned above should contain the image size. If the value of the addresses mentioned above is neither 0x0 nor 0xFFFFFFFF, then the boot will proceed else it will move to the next sector. If no image is found after checking four sectors, the ROM bootloader will move to the next device.

  • 0 in reply to Biser Gatchev-XID
    Expert 2985 points

    Hi Biser,

    Thank you for reply,

    SPL size for us is 25k, So if ROM Code is not validating SPL image,

    What is the purpose for ROM Code checking 4 sectors?

    Can we direct ROM code to look at some specific location by putting some magic number??

    1. Basically i am tring to understand if we have to keep 4 redudant copies then how can we direct ROM code to check another copy of SPL if first one is corrupted ?

    2. Do you suggest us to keep 4 copies of SPL or one in SPI NOR. Is SPI NOR realiable to avoid 4 redundant copies ?

    like UBL code, is ROM Code for am335x available for us to look at? if yes can you share link for the same ?

    Thank you,

    Regards,

    Ankur

  • 0 in reply to Ankur Tank
    TI__Guru**** 393215 points

    Hi Ankur,

    NOR flash technology is completely different from NAND flash. It doesn't have the tendency for bit-flip errors that NAND has and data retention is completely reliable under device recommended operating conditions. Therefore there is no ECC required for NOR flashes and redundant copies of SPL are unnecessary.

    As for AM335X ROM code, that's not available.

  • 0 in reply to Biser Gatchev-XID
    Expert 2985 points

    Hi Biser,

    Thank you very much for reply, it will help us finalize our design.

    One last question about ROM Code,

    Why ROM Code checks for 4 sectors on the SPI NOR flash ? 

    Is it providing any design advantage ? i am curious about that.

    Thank you,

    Regards,

    Ankur

  • 0 in reply to Ankur Tank
    TI__Guru**** 393215 points

    I don't have access to the ROM code to give a precise answer, but it may well be that the same code fragment is used for NAND boot too, where there are also 4 sectors checked.

  • 0 in reply to Biser Gatchev-XID
    Expert 2985 points

    Thank you for reply Biser,

    In which forum should I post this last question? any suggestions ?

    Thank you,

    Regards,

    Ankur

  • 0 in reply to Ankur Tank
    TI__Guru**** 393215 points

    I don't understand, what is your last question?

  • 0 in reply to Biser Gatchev-XID
    Expert 2985 points

    Hi Biser,

    Apologies for not being clear enough,

    By last question I meant the question I had asked in my previous reply,

    i.e.

    "Why ROM Code checks for 4 sectors on the SPI NOR flash ?

    Is it providing any design advantage ? i am curious about that."


    Thank you,

    Regards,
    Ankur

  • 0 in reply to Ankur Tank
    TI__Guru**** 393215 points

    OK, maybe my answer was not clear enough. The 4 sectors method is used in NAND flash boot. NAND technology tends to have bit-flip errors, therefore 4 redundant copies of the MLO are kept. I suppose the same ROM code subroutines are used for SPI flash too. ROM code is however not available to check, so this is only my guess.