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GPMC Dynamically switching between SYNC mode and Async mode

Other Parts Discussed in Thread: TMS320DM8148

Hi,

In our design we are using DM8148. We are planning to use GPMC for the data transfer between FPGA and 8148. We have following queries regarding GPMC frequency.

  1. According to Data sheet TMS320DM8148.pdf table- 8.35 the maximum frequency possible by the GPMC in synchronous mode is 50 MHz. But according to Technical Reference Manual section 11.4.1.3 GPMC can operate at 100 MHz in synchronous mode also. Which is the correct? As per my understanding GPMC is connected to sys_clk6. By configuring GPMCFCLKDIVIDER=0 I can get GPMC to run at 100 MHz in synchronous mode also. Am I Correct ??

  2. I have two devices on GPMC bus, FPGA and Flash. I would like to operate FPGA in sync mode and flash in async mode. Both FPGA and Flash needs to be accessed randomly.Apart from Boot up Flash is also  used to store some user data at run time.  As per 8148 TRM, we can configure all the parameters separately for each slave. 
    Can I configure one slave (Flash) in async mode and other slave (FPGA) in sync mode? 
    Is it possible to switch between aync and sync mode, in run time based on Flash access and FPGA access? 
  • Hello,

    kashetty said:
    According to Data sheet TMS320DM8148.pdf table- 8.35 the maximum frequency possible by the GPMC in synchronous mode is 50 MHz. But according to Technical Reference Manual section 11.4.1.3 GPMC can operate at 100 MHz in synchronous mode also. Which is the correct?

    50Mhz is the output clock of the GPMC (at pin GPMC_CLK), while 100MHz is the input clock of the GPMC, input from the device PRCM.

    BR
    Pavel

  • Hi Pavel,

     Thanx for the reply. The input clk to GPMC i.e GPMC_FCLK is 100 MHz. If  I keep my GPMCFCLKDIVIDER bit as 0, then GPMC_CLK= GPMC_FCLK. So Can I get 100 MHz from output of GPMC ??

  • EDIT:

    After additional investigation, I should edit my post. The DM814x datasheet is correct, the max frequency on the GPMC_CLK pin is 50MHz, which corresponds to min period of 20ns. All this in sync mode. In async mode, there is no clock signal on the GPMC_CLK pin.


    BR
    Pavel

  • kashetty said:
    • I have two devices on GPMC bus, FPGA and Flash. I would like to operate FPGA in sync mode and flash in async mode. Both FPGA and Flash needs to be accessed randomly.Apart from Boot up Flash is also  used to store some user data at run time.  As per 8148 TRM, we can configure all the parameters separately for each slave. 
      Can I configure one slave (Flash) in async mode and other slave (FPGA) in sync mode? 
      Is it possible to switch between aync and sync mode, in run time based on Flash access and FPGA access? 

    Yes, I think this should be possible (async/Flash on CSx and sync/FPGA on CSy). See the below e2e threads for info:

     

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/142450

  • Hi Pavel,
    Small Correction. In async mode there is no clock singal on GPMC_CLK pin
  • Hi Pavel,
    Thanks for reply. I referred to the links you posted. But my question is different from theirs. My question is at the same time can I connect A Sync device and an Async device to GPMC. Can GPMC can switch dynamically between Sync and Async mode at run time. I did n't find answer to my question in those post.
  • kashetty said:
    In async mode there is no clock singal on GPMC_CLK pin

    Correct. I edit my post.

    BR
    Pavel

  • kashetty said:
    My question is at the same time can I connect A Sync device and an Async device to GPMC. Can GPMC can switch dynamically between Sync and Async mode at run time.

    I think this is possible. I will double check this with our GPMC experts and update this thread when I have something more.

    BR
    Pavel

  • Hi Pavel,
    " The DM814x datasheet is correct, the max frequency on the GPMC_CLK pin is 50MHz, which corresponds to min period of 20ns. All this in sync mode. " Does this mean that in Sync mode GPMC_FCLK( Input clk to GPMC from PCRM) can be 100MHz but GPMC_CLK (Clk from GPMC to External device) is max 50MHz ??
  • kashetty said:
    Does this mean that in Sync mode GPMC_FCLK( Input clk to GPMC from PCRM) can be 100MHz but GPMC_CLK (Clk from GPMC to External device) is max 50MHz ??

    Yes.

    BR
    Pavel

  • If that so, if I keep GPMCFCLKDIVIDER = 0 , then theoretically GPMC_CLK should be equal to GPMC_FCLK. Do you mean to say I can't keep GPMCFCLKDIVIDER bit as 0 ??
  • kashetty said:
    If that so, if I keep GPMCFCLKDIVIDER = 0 , then theoretically GPMC_CLK should be equal to GPMC_FCLK. Do you mean to say I can't keep GPMCFCLKDIVIDER bit as 0 ??

    I think you can keep it to 0, but the result will be same as setting it to 1 (/2), the GPMC_CLK will be 50MHz. You can attach a scope to that pin and see what the result would be.

    BR
    Pavel

  • kashetty said:
    My question is at the same time can I connect A Sync device and an Async device to GPMC. Can GPMC can switch dynamically between Sync and Async mode at run time.

    The answer from the GPMC team:

    Yes.  You can dynamically switch between async and sync modes during runtime.  Just make sure the GPMC_CONFIG registers for both Chip Selects are setup properly for faster switching.

  • Hi Pavel,
    Thanks for the Help. I have further two more questions on GPMC.
    1. GPMC interface supports both Address data multiplexed and Non multiplexed modes. According to TRM section 11.2.4.10.3.4 the protocol and timings for Non-multiplexed mode is similar to as multiplexed mode. In multiplexed mode since same pins are used for address and data, some cycles/clocks shall be used for Address Latching cycle. In Non-multiplexed mode as this Address latching cycle is not required, we should get more band width on GPMC. Can you please let me know the maximum achievable bandwidth in both multiplexed mode and non-multiplexed mode?
    2. Similar to my first question in this post (Dynamic switching between async and sync), can I switch dynamically between multiplexed and non- multiplexed mode at run time ??
  • Kashetty,

    kashetty said:
    1. GPMC interface supports both Address data multiplexed and Non multiplexed modes. According to TRM section 11.2.4.10.3.4 the protocol and timings for Non-multiplexed mode is similar to as multiplexed mode. In multiplexed mode since same pins are used for address and data, some cycles/clocks shall be used for Address Latching cycle. In Non-multiplexed mode as this Address latching cycle is not required, we should get more band width on GPMC. Can you please let me know the maximum achievable bandwidth in both multiplexed mode and non-multiplexed mode?

    I do not think we have such data. What I was able to find is that GPMC timing settings are defined to match the attached memory/device timing spec. For optimal NAND performance we should use prefetch and write post engine with DMA.

    See also the DM814x datasheet GPMC timing:

    8.8.2 GPMC Electrical Data/Timing - here we have timing for multiplexed and non-multiplexed mode

    See also the below wiki page (performance for NAND and NOR):

    kashetty said:
    2. Similar to my first question in this post (Dynamic switching between async and sync), can I switch dynamically between multiplexed and non- multiplexed mode at run time ??

    Yes, I think this should be possible.

    I will double check these questions with the GPMC team and come back to you with their opinion.

    Regards,
    Pavel