Load application from host to flash throug PCI bus

Mark,

Re: 1., I recommend that you probe the EMIF lines to measure the time between commands and compare that to the flash datasheet to ensure you are meeting timings.

Re: 2., I need to ask some clarifying questions.

a) Am I understanding correctly that you are trying to load code through PCI while the device is attempting to boot from an unprogrammed flash?

b) Please explain in more detail the steps you are taking to "stop processor, load loader, set PLL and other options".

c) When you "load loader", can you try reading it back to make sure that it was written correctly?

d) How are you issuing the command "start from entry point".  Are you reprogramming the DSPBOOTADDR to point to the loader in DDR and then issuing a software reset to the DSP?

Regards,

Brad

Hi Brad,

First of all thank you for attention.

BradCobb said:

Re: 1., I recommend that you probe the EMIF lines to measure the time between commands and compare that to the flash datasheet to ensure you are meeting timings.

Something mistical is here.

Performing the same program from emulator(DDR->flash) I can it run free and execute it step by step with the same result. So long delay between consequtive writes isn't problem.

I suppose the time between 2 writes through PCI bus to EMIF can not be shorter than 2 actions a(flash) =b(DDR). Last one is about 30 ns.

I tested different waits between sequantial writes. The same result.

BradCobb said:

a) Am I understanding correctly that you are trying to load code through PCI while the device is attempting to boot from an unprogrammed flash?

Yes, I need it. But I checked to write throug PCI bus for different DSP states. Result is the same.

BradCobb said:

b) Please explain in more detail the steps you are taking to "stop processor, load loader, set PLL and other options".

I use Sheldon's PassThrougRead/Write to communicate with DSP.

1 Read: DSP_RESET reg -> reset.   Write: reset&(~reset_mask) ->DSP_RESET reg. Stop DSP.

2 Read: BOOT reg -> boot.   Write: boot&(~boot_mask) ->BOOT reg. Clear BOOTCML bit

3 Write: BOOT_BASE ->DSP_BOOTADDR reg. Set BOOTADDR to BOOT_ROM

4 Write: 0x103 ->DSP_RESET reg. Activate DSP.

5. Set all you need here

6. Write loader to RAM

7 Write: entry_poin ->DSP_BOOTADDR reg. Set BOOTADDR to loader entry point

8 Write: BOOT_MASK ->DSP_BOOT reg. Start DSP

It is work when DSP started in PCI_BOOT_MODE and doesn,t in any other mode.

BradCobb said:

c) When you "load loader", can you try reading it back to make sure that it was written correctly?

Yes. I can check it reading throug PCI bus back and seeing it in emulator memory window.

BradCobb said:

d) How are you issuing the command "start from entry point".  Are you reprogramming the DSPBOOTADDR to point to the loader in DDR and then issuing a software reset to the DSP?

Steps 7 & 8 above. I played around trying many combinations. But ...

I have not any hardware debug tools right now. I hope to get digital scop next week.

Any ideas please.

Thank you for advance.

Mark

Mark,

What are the "BOOT reg" and "BOOTCML bit" in your step 2.?  Are you trying to write to the BOOTMODE field of the BOOTCFG register?  If so, this is a Read Only field and always reads back what was latched by the bootmode pins.  If you set the BOOTADDR to the Boot ROM address, then the ROM will always execute the boot mode specified by the bootmode pins.  In your case, since the bootmode pins are tied off to EMIF boot, so the DSP will begin booting from EMIF again in step 4.  If you need to execute the ROM PCI boot code instead, then the bootmode pins need to be changed to PCI boot.

Regards,

Brad

Hi Brad,

 I played with PCI bus modifying sample (LoadCoff_DM648) from Sheldon’s PCI bus driver. See comments from main file

      Function LoadCoff_DM648

            1. Soft reset DSP

            2. Clear BOOTCMPLT bit

            3. Set DSPBOOTADDR to BootROM

            4. Activate DSP

            5. Set Pll1 to 891 MHz

            6. Set Pll2 (DDR2) to 265.9 MHz

            7. Read COFF file and load programm to DSP

            8. Set programm entry point as DSP start address

            9. Tell DSP that COFF file is written (Run DSP from start address).

===========================================================================

      Steps preparing to load and loading program from COFF file to DSP

      1. Move Base Address of Region 1 to access DMA registers

            write DMAREG_BASE_ADDR(0x02800000) to PCIBAR1TRL (region 1)

      2. Clear BOOT bit and set BOOT addres to default

            2.1 Reset DSP(assert local reset)

                  Read data from MDCTL33(DSP_RESET = 0x00046A84[reg 2])

                  in our case it is 0x103 always

                  Clear bit 8 data &= ~DSP_RESET_mask(0x100)

                  Write data to MDCTL33(DSP_RESET = 0x00046A84[reg 2])

            2.2 Clear BOOT(0x1) bit in BOOTCMPLT(0x0004900C) register

                  Read data from BOOTCMPLT(BOOT = 0x0004900C[reg 2])

                  Clear bit 0 data &= ~BOOT_MASK(0x1)

                  Write data to BOOTCMPLT(BOOT = 0x0004900C[reg 2])

            2.3 Set DSPBOOTADDR to BootROM

                  Write BOOT_BASE(0x00800000) to DSPBOOTADDR(0x00049008[reg 2])

            2.4 Activate DSP(de-assert local reset)

                  Write 0x103 to MDCTL33(DSP_RESET = 0x00046A84[reg 2])

      3.    Set PLL1 to 891 MHG(multiplier=27, div2=3, div4=6)

            3.1 Set PLL to bypass mode

                  Read data from PLL1_PLLCTL(0x000E0100[reg 2])

                  Clear bit 5 data &= 0xffffffdf(~0x20)

                  Write data to PLL1_PLLCTL(0x000E0100[reg 2])

                  Clear bit 0 data &= 0xfffffffe(~0x1)

                  Write data to PLL1_PLLCTL(0x000E0100[reg 2])

            3.2 Configure and stabilize PLL

                  Set bit 3 data |= 0x8   // Reset PLL

                  Write data to PLL1_PLLCTL(0x000E0100[reg 2])

                  Read data from PLL1_PLLCTL(0x000E0100[reg 2])

                  if bit 1 is set(PLL is power down)

                        Set bit 4 data |= 0x10  // Disable PLL

                        Write data to PLL1_PLLCTL(0x000E0100[reg 2])

                        Clear bit 1 data &= 0xfffffffd(~0x2)      // Disable PLL

                        Write data to PLL1_PLLCTL(0x000E0100[reg 2])

                        Clear bit 4 data &= 0xffffffef(~0x10)     // Enable PLL

                        Write data to PLL1_PLLCTL(0x000E0100[reg 2])

                  else (PLL is power down)

                        Clear bit 4 data &= 0xffffffef(~0x10)     // Enable PLL

                        Write data to PLL1_PLLCTL(0x000E0100[reg 2])

            3.3 Set PLL multiplier register (minus 1 desired mult value)

                  Write mult value - 1 to PLL1_PLLM(0x000E0110[reg 2])

            3.4 Set PLL post dividers (minus 1 desired div value)

                  Write (0x8000) | (div2 - 1) to PLL1_DIV2(0x000E011C[reg 2])

                  Write (0x8000) | (div4 - 1) to PLL1_DIV4(0x000E0160[reg 2])

            3.5 Start transition(set GO[0] bit in PLL1_CMD)

                  Read data from PLL1_CMD(0x000E0138[reg 2])

                  Set bit 0 data |= 0x1   // GO

                  Write data to PLL1_CMD(0x000E0138[reg 2])

            3.6 Wait for complition of transition(GO[0] bit in PLL1_STAT will be cleared)

                  Periodically read data from PLL1_STAT(0x000E013C[reg 2])

                  and check bit 0(GO[0])

            3.7 Release PLL from reset

                  Read data from PLL1_PLLCTL(0x000E0100[reg 2])

                  Clear bit 3 data &= 0xFFFFFFF7(~0x8)

                  Write data to PLL1_PLLCTL(0x000E0100[reg 2])

            3.8 Set PLL to PLL mode

                  Set bit 0 data |= 0x1   // Enable PLL

                  Write data to PLL1_PLLCTL(0x000E0100[reg 2])

      4.    Set PLL2(DDR2) to 265.9 MHG(fr=265909070)

      5.    Load program from COFF file

      6.    Write program entry point to BOOT address and run DSP(Set BOOT bit)

                  Write entry point of program to DSPBOOTADDR(0x00049008[reg 2])

                  Write BOOT_MASK(0x1) to BOOTCMPLT(BOOT = 0x0004900C[reg 2])

 ===========================================================================

The problem is in what BOOT_MODE DSP started (pin configuration). If it was PCI_BOOT_MODE all is perfect.

I can’t run DSP (equivalent p.6 in comment above) in any other BOOT_MODE. Perform other steps isn’t problem.

You can put all things that you need including entry point set. And stop. How to push processor?

It doesn’t understand that BOOT bit is set.

Mark

Mark,

Writing to the BOOTCMPLT register in your step 6. will not kick off the DSP when  the ROM is executing the EMIF boot mode.  The BOOTCMPLT register is only used by host boot modes like PCI.  Try resetting the DSP in step 6. instead of writing to the BOOTCMPLT register.  When the DSP comes out of reset, it should start executing from your program entry point programmed in the DSPBOOTADDR register.

Regards,

Brad

Hi Brad,

Is it mean I shoud perform 4 steps from example again?

        1. Soft reset DSP

        2. Clear BOOTCMPLT bit

        3. Set DSPBOOTADDR to BootROM

        4. Activate DSP

I have tryed something similar and processor didn't run

Can you put more details?

Mark

Mark,

Only do steps 1. and 4.  If you reprogram the DSPBOOTADDR to BootROM, then the DSP will start executing the EMIF boot mode again instead of your loader.

Regards,

Brad

Thank you Brad.

I will try it now.

Mark