EDMA pauses

Iaroslav Ianishyn

Hello!

We have used four memory bus masters: EDMA0_0 for McBSP (permanent), EDMA0_1 for SPI (frequent-periodic), EDMA1 for manual periodic big data block transfers, and also there is DSP.

There is a problem: on some pick loads EDMA0_1 is not in time to fill in SPI TX. As far as we see, memory bus is overloaded with accesses and EDMA TRs encounters delays from time to time.

Solution can be: "pause" EDMA1 transfers while SPI communication is performing (SS asserted): this timing is not critical for EDMA1 transfers.

But here is a problem too: EDMA1 holds not one, but few transfers, some of them are consecutive, some intended to be "parallel", some are a bit complicated executing sorting, and actually a full power of linking and chaining is used. So manual implementation of "EDMA scheduler" still is possible, but is very complicated.

Question: maybe there is an easy way/trick to just "pause" EDMA CC/TC and then "resume" so it just continues with it's previous job (although I don't see this is TRM)? Because, as I understand, if just disable channel in the middle of the transfer, and then enable with pushing manual start again - this will not work, or at least we're risking to lose some events. And anyway whole EDMA1 at one pausing is preferable.

over 10 years ago

0 Sivaraj Kuppuraj over 10 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

I don't think, there are EDMA driver API calls to pause and resume the EDMA CC/TC. May be, you could have flexibility to change the EDMA transfer triggering mode by disabling the DMA channel which was previously triggered in some other modes (event, manual, qdma) and enable the same DMA channel by changing the EDMA trigger mode. I mean, you could dynamically change the EDMA transfer triggering mode and schedule the EDMA TR's accordingly in the CC event queue based on the high priority service requests mapped to some master peripherals and dynamically change the TR's based on the priorities configured for different servicing peripherals in the EDMA CC queue priority register (QUEPRI) as well configuring the master priority 2 registers (MSTPRI2) for EDMA TC's in the SYSCFG module.

Kindly check the below EDMA driver API's to schedule EDMA TR's through variably tuning the triggering modes to manual/event based on the traffic load requirement on SPI buses;

EDMA3RequestChannel, EDMA3FreeChannel, EDMA3EnableTransfer, EDMA3DisableTransfer

Also, make sure that the TC priority for Queue/TC servicing the SPI peripheral is at higher priority than the TC servicing the EMIFA/DDR (memory to memory related transfers)

Please refer sections 18.2.13.1, 18.2.13.4, 18.2.4.1 to know more details on EDMA2 priority assignments and system priority considerations on TC's

http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

For using EDMA3, there are very good online c6000 embedded workshop videos available in the below wiki:

http://processors.wiki.ti.com/index.php/C6000_Embedded_Design_Workshop_Using_BIOS#C6000_Architecture_Specific_Topics

To understand how tasks are configured and prioritized in bios scheduler, please see Chapter 8 on the online wiki video download link, which is part of TI RTOS kernel workshop video tutorial as below:

http://processors.wiki.ti.com/index.php/TI-RTOS_Workshop

Thanks & regards,

Sivaraj K

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EDMA pauses