DM368 GPIOs 61,62

Pete Eberlein

Hello, I am trying to use the GPIO 61 and 62 on our design using the DM368 processor, but I'm not seeing the correct signal on the pin. I have configured them as outputs, and other GPIOs in bank 2 work ok. The GIO[57..64] are muxed with AEMIF EM_D[8..15], but we are using the 8-bit AEMIF interface for boot. The BOOTCFG register is 0x00000032, which means AECFG is 010, and so the GIO[57..64] should be enabled. Please tell me something I missed to enable those GPIOs, or any other suggestions?

over 11 years ago

0 1330hayacool7102 over 11 years ago

Guru 10655 points

Are these two pins used for other features originally? if so, did you remove the related control?

0 Pete Eberlein over 11 years ago in reply to 1330hayacool7102

Intellectual 580 points

They are not used for anything else. We are only using the 8-bit data bus for AEMIF, and want to use the GIO[57..64] pins.

0 1330hayacool7102 over 11 years ago in reply to Pete Eberlein

Guru 10655 points

did you mean you test two GPIO manually after boot-up? if so, could you verify the configuration like PINMUX/BOOTCFG before setting GPIO?

0 Pete Eberlein over 11 years ago in reply to 1330hayacool7102

Intellectual 580 points

PINMUX0=00fe0000
PINMUX1=00005555
PINMUX2=00000056
PINMUX3=00560000
PINMUX4=aa8c0000
BOOTCFG=00000032

Like I said before, the BOOTCFG:AECFG is 010, so according to Table 85 "Async EMIF Configuration (AECFG) Pin Mux Coding" it should be selecting GIO[57..64] for the pin mux.

I have discovered that the signals on those pins do change when I write to the EMIF, leading me to believe that the EM_D[8..15] is selected despite the AECFG setting.

0 Pete Eberlein over 11 years ago in reply to Pete Eberlein

Intellectual 580 points

Aha, I overlooked the PINMUX2:EM_D[15:8] setting, and of course it is set to 1. Then I found we had this in the kernel:

davinci_cfg_reg(DM365_AEMIF_D15_8);

Removing this line solved the problem.

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DM368 GPIOs 61,62