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C6657: is a DDR interface reinit required after PLL reinit

Iain Rist
Prodigy 80 points

On my C6657 I am required to conditionally increase the core clock frequency at application startup. By the time I am told to perform this change I already have a configured DDR interface which I am using.

Does changing the core clock frequency (reconfiguring the PLL) bring down the DDR interface?

Thanks,

Iain

  • 0
    TI__Mastermind 43660 points

    Hello Iain,

    Since there is a separate PLL available for DDR3 with separate reference clock, changing the core clock frequency (Main PLL reconfiguration) would not affect the DDR3 interface. The DDR3 PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high.

    But please make sure no DDR3 accesses will be performed during main PLL reconfiguration.

    Regards,
    Senthil