I am using the K2E_EVM as a starting point for a K2E based hardware design, and it is not clear how I should control the Power Sequencer (U4, UCD9090). I am assuming the power sequencer needs to be programmed prior to initial processor power up; is this correct? Also, referrring to the K2E_EVM schematic, the source of the input I2C bus to U4 Power Sequencer (UCD9090), comprised of nets PW_SEQ_SCL and PW_SEQ_SDA, appears to be selectable so that the sequencer can be accessed by the BMC, the K2E I2C, or the K2E Smart Reflex. The BMC appears to be controlling which of these entities is currently connected to the power sequencer. In my design, the BMC will not be used. How should the sequencer be controlled in this case? Do I need to allow both K2E I2C and SmartReflex I2C access to this interface? What should determine which entity should be accessing the sequencer via the I2C at any given time? I am assuming that the SmartReflex section should control/monitor the power up sequence. Is the K2E I2C section possibly only used for status? Is there any documentation that explains this in-depth?