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GPMC CS base address

Steven Weng1
Expert 2200 points
Other Parts Discussed in Thread: TMS320DM8168

Hi,

There are two gpmc device on our board.

CS0 - Nand flash

CS3 - Non-multiplexed attached device(8-bit)

In TRM, GPMC_CONFIG7[5:0] corresponds to A29, A28, A27, A26, A25, and A24

nand flash CS0 GPMC_CONFIG[5:0] = 8 and non-multiplexed attached device CS3 GPMC_CONFIG[5:0] = 1, So the base address will be 0x8000000 in nand flash and 0x1000000 in non-multiplexed attached device...

In TRM,

The GPMC 512 Mbyte address space can be divided into a maximum of eight chip-select regions with
programmable base address and programmable CS size. The CS size is programmable from 16 Mbytes
to 256 Mbytes (must be a power-of-2) and is defined by the mask field. Attached memory smaller than the
programmed CS region size is accessed through the entire CS region (aliasing).

1) Does it mean maximum capacity of the attached device up to 256Mbytes and determined in GPMC_CONFIG7_i[7-0] BASEADDRESS bit field and GPMC_CONFIG7_i[11-8] MASKADDRESS bit field ?

2) How about nand flash, is it differenet? GPMC_CONFIG7 = 0xF48 in nand flash CS0, it means base address 0x80000000 and CS size 16Mbytes but our nand flash is 256Mbytes?

3) GPMC address space L3 mapping in 0x00000000 ~ 0x1FFFFFFF, Could I use 0x00000000 as start address for the attached device?

Sorry for many questions, any helps will be appreciate!

thank you

BR,

Steven

  • 0
    TI__Guru**** 170625 points

    Steven,

    Steven Weng1 said:
    1) Does it mean maximum capacity of the attached device up to 256Mbytes and determined in GPMC_CONFIG7_i[7-0] BASEADDRESS bit field and GPMC_CONFIG7_i[11-8] MASKADDRESS bit field ?

    Yes, max capacity of the attached device is up to 256MBytes, determined by GPMC_CONFIG7_i[5:0] BASEADDRESS and GPMC_CONFIG7_i[11:8] MASKADDRESS.

    See the below e2e threads for more info:

    Steven Weng1 said:
    2) How about nand flash, is it differenet? GPMC_CONFIG7 = 0xF48 in nand flash CS0, it means base address 0x80000000 and CS size 16Mbytes but our nand flash is 256Mbytes?

    Note that this 256MByte max size per chip select restriction is for memory mapped peripheral. NAND memory chip is not memory mapped, it is accessed through registers of the GPMC module, thus higher than 256MBytes size NAND chips can be used. For more details see below e2e threads:

     

    Steven Weng1 said:
    3) GPMC address space L3 mapping in 0x00000000 ~ 0x1FFFFFFF, Could I use 0x00000000 as start address for the attached device?

    No, the first section of GPMC memory (0x0 - 0x00FF_FFFF) is reserved for BOOTROM (ROM Code). Accessible memory starts at location 0x0100_0000. See DM816x datasheet, memory map.


    See also if the below e2e threads will be in help:

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Expert 2200 points
    Hi Pavel,
    Thank for the detailed reply. Thanks very much!!!
    The L3 memory map is different in TRM(sprugx8.pdf) and datasheet(tms320dm8168.pdf)
    I will refer to the datasheet....
    Thank again!
    Steven