[C6655, IBL] What this code is ?

Naoki Kawada

Guru 19890 points

Hi,

I have a quick question about IBL code for C6655.
I'm now digging the IBL code deployed in MCSDK v2_01_02_06 in order to understand what IBL does in boot process.
I almost understand its process, but I don't understand the following code in iblinit.c:

    if (IBL_ENABLE_EDC)
    {
        iblEnableEDC ();
    }

    /* Check if need to enter Rom boot loader again */
    if (IBL_ENTER_ROM)
    {
        iblEnterRom ();
    }

IBL_ENABLE_EDC and IBL_ENTER_ROM looks enabled in /src/device/c665x/target.h

/**
* @brief
* Support for PLL workaround to re-enter ROM boot loader.
*/
#define IBL_ENTER_ROM 1

/**
* @brief
* Support for enabling EDC for internal memory.
*/
#define IBL_ENABLE_EDC 1

What is your intention for ?
Is this something workaround code only for EVM ? Can we remove these code for the target board ?

Background:
My customer is now developing their target board with C6655.
I'm thinking that I suggest my customer to use C6657's IBL for the boot process on their target board.
(I believe C6657's IBL can be also used for C6655, If my understanding is not correct, please correct me.)

Best Regards,
Kawada

over 10 years ago

0 Raja over 10 years ago

TI__Guru* 81335 points

Yes. Your understanding is correct. The C6657's IBL can be used for C6655.

iblEnableEDC() is to enable error detection and correction enable on internal memories like L1 & L2.
From my understaning, iblEnterRom() is the PLL workaround for for non-I2C boot modes.

Thank you.

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

Yes, your understanding is correct. User can use the C6657 IBL code for C6655 device.

Thanks,

0 Naoki Kawada over 10 years ago in reply to Ganapathi Dhandapani95

Guru 19890 points

Hi Rajasekaran K and Ganapathi,

Thanks for your help. iblEnterRom for c6657 looks like :

/**
 * @brief
 *      Enter the ROM boot loader if the FPGA boot register
 *      indicates it was not I2C address 0x51 boot, this is necessary
 *      to apply the PLL workaround for non-I2C boot modes
 */
void iblEnterRom ()
{
    uint32      v, dev_stat, bm_lo, bm_hi;
    void        (*exit)();

	
    /* Reset SPI */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);

    /* Release Reset */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_ENABLE);

    /* CS1, CLK, in and out are functional pins, FPGA uses SPI CS1 */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIPC0, 0xe02);

    /* prescale=7, char len=16 */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIFMT(0), 0x710);

    /* C2TDELAY=0x6, T2CDELAY=0x3 */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIDELAY, 0x6030000);

    /* Clear the SPIDAT0 */
    //DEVICE_REG32_R (DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0);

As you see, this code is very specific to C6657 EVM... So, we will skip this code for the actual target board.

Now let me confirm one more thing about PLL configurations in IBL.
We are now assuming I2C/SPI master boot on the target board. In this mode, RBL does not lock system PLL automatically. So IBL should do this task instead.
IBL has already had an entry for this:

/**
 * @brief Configure the PLLs
 *
 * @details
 *   The three PLLs are enabled. Only the main PLL has the ability to configure
 *   the multiplier and dividers.
 */
void devicePllConfig (void)
{
    /* Unlock the chip registers and leave them unlocked */
    *((Uint32 *)0x2620038) = 0x83e70b13;
    *((Uint32 *)0x262003c) = 0x95a4f1e0;

    if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
        hwPllSetPll (MAIN_PLL, 
                     ibl.pllConfig[ibl_MAIN_PLL].prediv,
                     ibl.pllConfig[ibl_MAIN_PLL].mult,
                     ibl.pllConfig[ibl_MAIN_PLL].postdiv);

    if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
        hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
                         ibl.pllConfig[ibl_DDR_PLL].prediv,
                         ibl.pllConfig[ibl_DDR_PLL].mult,
                         ibl.pllConfig[ibl_DDR_PLL].postdiv,
                         ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
                         ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);

}

What I'm concerning is, the errata says that PLL should be configured twice. So, should I call this function twice ?
Please take a look at the following section in errata:
Usage Note 9 Minimizing Main PLL Jitter Usage Note

Also, PLL configuration sequence looks different from the sequence described in http://www.ti.com/lit/ug/sprugv2f/sprugv2f.pdf

The errata also says that PLL configuration sequence should follow this manual. This is described in Usage Note 13 Revised PLL Programming Sequence Usage Note. Should we modify IBL implementation to meet this requirement ?

Best Regards,
Kawada

Processors

Processors forum

[C6655, IBL] What this code is ?