Hi,
Please take a look at C6655 data sheet.
2.5.3 PLL Boot Configuration Settings
In this table, the default setting of PLLD and PLLM registers seems to be defined by BOOTMODE pins, assuming "Input Clock Freq". These are 50.00/66.67/80.00/100.00/156.25/250.00/312.50/122.88 Mhz.
My understanding is that...
1. this table defines just default values of PLLD/PLLM assuming the above pre-defined input clock frequency and ROM Bootloader *never* configures PLL with them. Configuring MAIN PLL is user's option in IBL.
2. So, user can use another value for input clock freq if it meets the requirement described in 7.5.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing, i.e., 3.2ns(min)/25ns(max)
Is my understanding correct ?
Best Regards,
Kawada