Hi, I'm trying to swap the transport layer of MessageQ from Shared Memory with QMSS and I'm experiencing problems when I declare less descriptors than the bench-marking example code found in the pdk folder.
I found a post that describes one of the problems I'm seeing and I suspect is from the same cause. Specifically the loss of coherence between L1D cache and L2 cache.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/311613/1371556#1371556
I'm also seeing QMSS initialization errors and hangs on MessageQ_put().
These problems all go away when I keep the number of descriptors high. I was wondering if someone could comment on whether the problem cited by the previous post has a fix.
Best Regards,
Chia-Ning Wang