66AK2H12 SRIO packet priority

Some of those references, especially the wiki stuff, is referring to C64x. C66x was enhanced in many areas.

Q1. Do the SWRITE, NWRITE and NWRITE_R packets handled correctly when port A and port B receive packets at the same time which containing same SRCID?
I am minding if port A or B returns the wrong response to the other, when both ports are recieved packet containing same SRCID.


ANSWER: For non-posted request packets, the corresponding outbound response packet will always be sent out on the same port the request came in on. The port is maintained and we simply swap the SRCID and DESTID of the request for the outbound response.

Q2. If multiple ports receive packets containing the same SRCID, dose the following constrain in SRIO UG consider
the receiving ports? That means that SRIO peripheral handles these packets as "same SRCID transaction" or NOT.

ANSWER: The text you highlighted in RED is for the LSU, which is a logical layer transmitting block. It has nothing to do with RX ports. The LSU can send/track 16 outstanding packets at a time that are part of one transaction. For example, you program the LSU to send 4KB, it will blast out 16 256B packets as fast as it can, without waiting for any reponses. However, it will not move to the next LSU shadow register until all responses of the preceding transaction are recieved. If two separate LSUs try to reuse the same SRCID/DESTID pair, it will also wait until the first one is done.

Q3. When each ports receive the different priority packet at same time:
　Q3-1. Does high-priority packet be processed at first? If so, could you explain the scheduling scheme among multiple ports?
Q3-2. During processing the lower priority packet, when does the SRIO peripheral switch to the higher packet?

ANSWER: In C66x devices, the physical layer RX ports attempt to pass their packets to the logical layer in the following manner.
- there are RX buffer thresholds for each priority in both the physical layer and logical layer
- each port will re-order packets and pass the highest priority packet to the logical layer. The thresholds determine if the highest priority packet for that port is able to be sent.
- the physical layer RX state machine will round robin between ports, always attempting to send that port's highest priority packet to the logical layer. If it can't it moves on in the round robin.

Also note that all packet handling is done at a packet boundary. It handles one packet then moves on in the state machine. Also note that once the packets are in the RX shared buffer, they are handed to the protocol blocks (i.e. MAU, LSU, RXU, TXU, etc) based on priority as well.

Regards,
Travis

2) The post you mentioned says as follows:

"If a read/write request comes in with a same SrcID, same DestID, and same or lower Priority as

any pending transaction (pending completion status from DMA), then the MAU is stalled at this point to

wait until those outstanding transactions (of same IDs, =< pri) are completed. "

We would like to clarify this description.

If SRIO peripheral receives posted-write type packets (SWRITE or NWRITE) continuously,

with same SrcID/DestID/Priority, dose MAU stall until previous posted-write request reaches

to final destination memory(such as DDR)? If yes, we think such mechanism impacts throughput negatively.

ANSWER:  Correct, this is the functionality that was built in to the SRIO peripheral in order to maintain SRIO priority ordering on the chip.  What you have to remember is that the DMA bandwidth is very large, so the affects on the SRIO throughput are not huge.  If you take a look at the measured SRIO throughput performance in: http://www.ti.com/lit/an/sprabk5a/sprabk5a.pdf

the number reflect the performance while using the same SRCID/DESTID on posted transactions.

Regards,

Travis