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Some questions about the PCIE MSI interrupt between DM8168 and c6678

      Hi ,all:

       I  use DM8168 as RC and C6678 as EP.   Now I can transfer data between EP and RC.But when EP sends MSI to RC,the RC cannot response to the MSI Interupt. this is the configure of RC and EP .

       when the link is up,  the MSI associated Registers in EP side is:         

              [C66xx_0] Status Command register is 0x100540 
              [C66xx_0] MSI_CAP  raw is 0x817005
              [C66xx_0] MSI_LOW32 raw is 0x51000054 
              [C66xx_0] MSI_UP32 register is 0x0 
              [C66xx_0] MSI_DATA register is 0x0

      RC:

               BAR0 is 0x51000000

               MSI0_IRQ_ENABLE_SET  is 0xFFFFFFFF   and MSI0_IRQ_ENABLE_CLR  is 0x0;

               then insmod ep driver,lspic -v,the infomation is :

00:00.0 Class 0604: Device 104c:b800 (rev 01) 
               Flags: bus master, fast devsel, latency 0 
               Memory at <ignored> (32-bit, non-prefetchable) 
               Memory at <ignored> (32-bit, prefetchable) 
               Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 
               Memory behind bridge: 20000000-200fffff 
               Prefetchable memory behind bridge: 20100000-201fffff 
              Capabilities: [40] Power Management version 3 
              Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ 
              Capabilities: [70] Express Root Port (Slot-), MSI 00 
              Capabilities: [100] Advanced Error Reporting 

01:00.0 Class 0000: Device 104c:8888 (rev 01) 
               Flags: bus master, fast devsel, latency 0, IRQ 368 
               Memory at 21800000 (32-bit, non-prefetchable) [size=2K] 
               Memory at 20000000 (32-bit, prefetchable) [size=2K] 
               Memory at <unassigned> (32-bit, prefetchable) 
               Memory at <unassigned> (32-bit, prefetchable) 
               Capabilities: [40] Power Management version 3 
               Capabilities: [50] MSI: Enable+ Count=1/32 Maskable- 64bit- 
               Capabilities: [70] Express Endpoint, MSI 00 
               Capabilities: [100] Advanced Error Reporting

               then I send MSI from EP to RC: *((volatile uint32_t *) 0x60000054) = 0x00,though Outbound Address Translation,I am sure that  the address of the TLP is 0x51000054, and I check the the MSI associated Registers in RC side,

               the MSI_IRQ value is 0 
               the MSI0_IRQ_STATUS value is 0 
               the MSI0_IRQ_ENABLE_SET value is ffffffff 
               the MSI0_IRQ_ENABLE_CLR value is ffffffff 
               the IRQ_STATUS value is 0 
               the IRQ_ENABLE_SET value is f 
               the IRQ_ENABLE_CLR value is f 

      the  MSI0_IRQ_STATUS Register is 0,  which  indicates  the MSI  interrupt is not  triggered.

      Is there anything wrong in my configurations? and how can I resolve it?  

Sincerely,

sichang

  • Hi Sichang,

    Are you using EZSDK or DVR RDK?

    Please switch to the latest kernel version.

    In case of EZSDK:
    http://arago-project.org/git/projects/?p=linux-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    In case of DVR RDK:
    http://arago-project.org/git/projects/?p=linux-dvr-rdk-dm81xx.git;a=shortlog;h=refs/heads/dvrrdk_kernel_int_branch

    Are you aligned with the below wiki page?
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Root_Complex_Driver_User_Guide

    Make sure you have enabled MSI in linux kernel and in DM816x PCIe register MSI_CAP[16] MSI_EN=1

    Note that only Cortex-A8 ARM can receive MSI interrupt (PCIE_INT_I_INTR_PEND_N1) at irq number 49. See also DM816x TRM, section 17.2.9.3.2.1 MSI Interrupt Reception in RC Mode

    See also if the below e2e threads will be in help:
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/228415
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/126599
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/106374
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/124004
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/205356
    http://e2e.ti.com/support/embedded/linux/f/354/t/331133

    BR
    Pavel