66AK2H12 DDR3 leveling, write, read and gating delay

Hi,

As per the DDR3 Memory Controller User Guide.

After the DDR initial setting, all LCDL register fields are automatically updated by the VT compensation logic to track drifts due to voltage and temperature. The user can however override these values by writing to the respective fields of the register and/or optionally disabling the automatic drift compensation.

Refer section 4.65 DATX8 Local Calibrated Delay Line Register 0 (DXnLCDLR0) on DDR3 Memory Controller User Guide.

http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf

Thanks,

Hello H.U,

Q2. About DQS delay value:
How do I interpret DXnLCDLR1.RDQSD and WDQD values?
What picoseconds increase if calibration result value of WDQD plus 1?

For example, if calibration result value of WDQD is 0x12.
What picoseconds increase, when WDQD value is changed to 0x13.

The write data delay (WDQD) and the read DQS delay (RDQSD) are automatically derived from the measured period during calibration. After calibration WDQD and RDQSD fields will contain a value that corresponds to half the DDR clock period (or a quarter of the SDRAM clock period).

If the DDR3 operating frequency is 800MHz, the clock period is 1.25ns. So the WDQD and RDQSD register fields are loaded with the value equivalent to 0.625ns. By taking your example values, the one count increase corresponds to 34.722 picoseconds. This way you can calculate the timing for one count increase in these registers.

Regards,

Senthil