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DDR3 Paging Concept

Avinash Neethi1
Expert 2125 points

Other Parts Discussed in Thread: TMS320C6678

Dear All,

               We have made a customized Board using TMS320C6678 with 4GBit DDR3 Micron(MT41K256M16). 2GB capacity Total of 5chip(4Chip For 2GB capacity 1Chip for ECC). 

The Parameters Of the DDR3 Chip is Given Bellow:

Therefor the Page size is 2KB.

In KeyStone Architecture DDR3 Memory Controller(SPRUGV8D), 4.3 SDRAM Configuration Register(SDCFG),  BIT 0-2 Defines the Page Size.

Questions:

1. We have Configured the SDCFG Register to 2KB as per the DDR3 Datasheet. We can able the perform Read, write in DDR3 Correctly. But if we try to Load a program Through CCS we Can't?

2. We have Configured the SDCFG Register to 1KB as per the Column address. We can able the perform Read, write in DDR3 Correctly. But when we try to access the FULL 2GB there are certain data mismatch is occuring.

Any Suggestion to solve the above Issue.

  • 0
    Expert 2125 points

    The DDR3 Parameters are Bellow:

  • 0
    TI__Mastermind 43660 points

    Hello Avinash,

    Have you configured the other parameters correctly ? Could you please check your configuration register settings with respect to the below attached DDR3 register calculator.

    DDR3 Register Calc v4.xlsx

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Expert 2125 points

    Hi Senthil,

    I have configured All the Registers As per the TI DDR3 Register Calculation Excel sheet. I have also once again verified using your excel sheet too. Can you provide Why TI configuration is considering the Column Lines For Paging Instead of particular DDR3 Chip Page Size.

    Regards,

    Avinash N

  • 0 in reply to Avinash Neethi1
    TI__Mastermind 46460 points

    Avinash,

    Please refer to discussion about PAGESIZE in the DDR3 Memory Controller User Guide (SPRUGV8D).  Pagesize is used in the address translation.  It assumes x8 when choosing 1K or 2K.  Therefore, it is actually the number of column address bits.  In this SDRAM, that value is 10 so you need to choose 1K.

    You need to execute a DDR3 validity test to make sure that all locations can be accessed and that you know the size of the memory.  If you exceed the 2GB limit, the memory will alias back to the begining.  Once the controller is set-up, the full 2GB range should be contiguous and functional.  A simple test is to write the address value to all of the 32-bit locations in the 2GB memory and then to go back and verify that all of them are correct from the beginning to the end.

    Please provide details of the memory issue observed after programming the PAGESIZE correctly.

    Tom