Hello,
I’m writing to get information about topic is related to speed of PCIe interface. We are using PCIe interface of C6678 DSP. We have configured DSP as Root Complex and FPGA as End Point.
In the RC mode, we have configured to Gen2 speed of PCIe by setting the DIR_SPD field to 1 in Gen2 register (PL_GEN2). But, when we read this register after setting, we realized that DIR_SPD bit in the Gen2 register is always 0. Also, we have read all bits in the Gen2 register correctly except DIR_SPD bit. According to PCIe user guide (Sprugs6c), DIR_SPD bit in the Gen2 register is read/write bit.
Why we don't read DIR_SPD bit in the Gen2 register correctly? How can we solve this problem?
Thanks & best regards
Alican