Question about PLLCR of DDR3 module in 66AK2H12

GANG ZHANG48047

Other Parts Discussed in Thread: 66AK2H12

Hi, I can't find the meaning of ctl_clk and REF_CLK in the PLLCR register's field FRQSEL(bit 19-18) in page 4-52 of spruhn7a, can someone tell me? thanks.

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

ctl_clk/REF_CLK is Input DDR module clock. For more information refer 66AK2H12 Technical reference manual.

0 GANG ZHANG48047 over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 875 points

Hi, Ganapathi. Thanks for your reply. you said "ctl_clk/REF_CLK is Input DDR module clock", does it mean: the input clock frequency of DDR3 PLL? Can you tell me which Technical reference manual of 66AK2H12 should I refer in order to find the exact definition of ctl_clk and REF_CLK?

0 Senthilkumar Srinivasan over 10 years ago in reply to GANG ZHANG48047

TI__Mastermind 43660 points

Hello Gang,

Yes, it means the input clock to the DDR PLL.

You can refer section 10.6 DDR3A PLL and DDR3B PLL in the device datasheet for more details about DDR3 PLL.

http://www.ti.com/lit/ds/symlink/66ak2h12.pdf

The EVM technical reference manual is available in the below link.

http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd4.aspx

Regards,

Senthil

0 GANG ZHANG48047 over 10 years ago in reply to Senthilkumar Srinivasan

Intellectual 875 points

Hi, Senthil. Thanks for your reply. Is it DDRCLK(N|P) in Figure 10-25 in 66ak2h12.pdf ? In the evm, the input clock to DDR3A(B) is 100MHz, which is not in the range of ctl_clk/REF_CLK in PLLCR bit 19-18, its valid values are:

00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz

01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz

10 = Reserved

11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz

But 100MHz, is not in the range above. Did I misunderstand it? Can you give me more information about it? thanks.

0 Senthilkumar Srinivasan over 10 years ago in reply to GANG ZHANG48047

TI__Mastermind 43660 points

Hello Gang,

I am working with expert to get this answered. Due to holidays, the response will be delayed.

Regards,
Senthil

0 Senthilkumar Srinivasan over 10 years ago in reply to GANG ZHANG48047

TI__Mastermind 43660 points

Hello Gang,

Sorry for the misinterpretation. The ctl_clk/REF_CLK given in the FRQSEL field refers to DDR3 PHY reference clock and not DDR3 PLL reference clock.

It is the reference clock to the PHY which is half of the DDR clock and a quarter of the DDR data rate.

I will keep you posted if i get an information about FRQSEL field description change in user guide.

Regards,
Senthil

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Question about PLLCR of DDR3 module in 66AK2H12