How to config DSP Cache?

Refer to the following DSP mega module user guide and chapter 4.4.4

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprufk5&fileType=pdf

Hi Titus:

   Thanks very very much for your help!

   As in the document, I find that:

If you configure part of internal memory as cache, the L2 controller provides a means of writing back
changes made to its contents, or invalidating the cache's contents altogether. 

  So in my program, after processed frame data, I should call:

// cache write back
{
Cache_wbInv( dvp->stream, dvp->stream_length, Cache_Type_ALL, FALSE ) ;
}

to write back cache buffer to me. If I donn't call it,  it will get some wrong frame data.

But I had question that when I called Cache_wbInv, It will need about 230ms! So it is crazy thing.

Why?

Thanks very much!

Hi ChangSheng,

In CCS, options are available to configure the Cache through Graphical and text mode. Dynamic configuration is also seems to be possible.

http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache#Introduction

 

Regards,

Shankari

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Try to refer the following cache example from MCSDK package (CSL)

pdk_OMAPL138_1_01_00_01/packages/ti/csl/exampleProjects/cache_exampleProject/
pdk_OMAPL138_1_01_00_01/packages/ti/csl/omapl138-lcdk/examples/cache/src/cache_example.c

Thanks very much!