Hello
We are working on the PCB layout design based on 66AK2H12AAAW24 and TMS3206678ACYP25 DSP's.
According to the requirements defined in the "DDR3 Design Requirements for KeyStone Devices"
the traces shall be length-matched for +- 10mil for data and address lines.
Does the length-matching shall include the VIA's length?
Regards
