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How to do AM335x L2 ECC management?

Denny%20Yang99373
Expert 3805 points

Hi Team,

I have found the AM335x support L2 ECC. it can be enabled  by set CP15 register. But I can't find the ECC event on interrupt chapter.  

So How to know the times of  L2 error has been corrected or detected?  Are there any register to check?

And does this ECC can trigger the interrupt of ARM? 

Thanks!

BR,
Denny

  • 0
    TI__Guru**** 393215 points

    Hi Denny,

    There are no user available means to do what you want.

  • 0
    Mastermind 8040 points

    The Cortex-A8 doesn't seem to track how often a correctible (single-bit) error has occurred as far as I can tell. If an uncorrectable error is detected, a data- or prefetch-abort will be triggered, with the fault status register indicating a parity or ECC error. The cortex-A8 TRM advises that in this situation no recovery is possible and the abort handler should disable the caches, perform some final communication or logging of what happened, and reset the processor.

    Note BTW that bootrom initializes the processor with L1 parity and L2 parity/ECC disabled. Enabling L2 parity/ECC is relatively easy to do (you can choose between the two: ECC obviously being preferred for reliability, but it incurs a performance penality compared to just parity).  I haven't tried enabling L1 parity yet on an AM335x, but my attempts to do so on the related DM814x mostly led to a lot of frustration.