We are after some further help from TI with regard to McBSP synchronization.
We are looking to implement standard AES67 on our Ethernet network to give us low latency audio across devices. The i.MX6 can give us a sync pulse that is derived from the IEEE1588 clock. Our thoughts are to connect this to the FSR input of the McBSP for frame pulse synchronization of CLKS in generating internal CLKG as described in 2.5.3.4 of SPUHH0 guide. My question is that we have a CLKS of frequency 12.288MHZ whereas the 1588 synch pulse is high for a single 100MHz clock cycle, will this work? Is the FSR edge detected or triggered by an edge on CLKS?
