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BeagleBoneBlack (ARM3357) and PCM3168 clock signals issue

Pablo Fonovich
Intellectual 765 points
Other Parts Discussed in Thread: PCM3168

Hi:

Im designing a multichannel sound cape for the beaglebone black, using the PCM3168 audio codec...

My question is about clock signals...

So far, i have connected the sitara's mcasp0_aclkr (P9_42 on BBB) to the BCLKAD pin in the codec; the mcasp0_aclkx (P9_31) to the BCLKDA pin of the codec; mcasp0_fsr (P9_27) to the LRCLKAD of the codec and the mcasp0_fsx (P9_27) to the LRCLKDA of the codec.. Are this conections all right?

And what about the SCKI pin of the codec? where am i supposed to get the clock for that pin? i thought about the mcasp0_ahclkr or the mcasp0_ahclkx... what which one should i use?

And if someone has experience with the BeagleboneBlack, i would be grateful if you tell me if the headers pin's on the BBB i used (between brackets) are the correct ones...

Thanks very much

  • 0
    Intellectual 765 points
    Sorry... when i said "mcasp0_fsx (P9_27)" i meant "mcasp0_fsx (P9_29)"
  • 0 in reply to Pablo Fonovich
    TI__Guru**** 393215 points

    Hi Pablo,

    The functionality of the AM335X McASP pins is described in section 22 of the AM335X TRM Rev. K. BBB schematics can be found at http://elinux.org/Beagleboard:BeagleBoneBlack#Hardware_Files

  • 0
    Expert 1510 points

    This guide has lots of useful details about hooking up a codec to the McASP.  I'm not sure if you are using linux or not, but it will help either way.

  • 0 in reply to jelliott
    Intellectual 765 points

    Thanks very much...

    Yes i'm using linux, and this guide is going to be very usefull in the next stage of my design, but now my problem is more a hardware problem...

    I don't know if the System Clock Input (SCKI) of the PCM3168 should be connected directly to one of the mcasp0 pins, and to which pin.

    I've already looked up in the datasheets, but i can't find any straight answer...

    I also asked if the other conections where OK just to be sure, cause what i've found out in the datasheets led me to do that conections... Only the SCKI i don't know where to get it...

    Thanks very much

  • 0 in reply to Pablo Fonovich
    Expert 1510 points

    It looks like SCKI corresponds to MCLK; you could either have it sourced by the the McASP0 MCLK or from an external oscillator.  On most sitara EVMs, MCLK for the codec is sourced by an external oscillator.  Here is an example.  I would recommend taking a look at the Sitara SDK Audio page as a whole, as it should help out with the process of connecting a device to the the McASP.

    You may want to ask about the best configuration for the PCM3178 for your application on the Audio Codec forums, too.

  • 0 in reply to jelliott
    Intellectual 765 points
    Thanks very much...
    I will look at the links you suggested, and i will make a post in the audio forum...
    I think i will use an external oscilator...
    Thanks again
  • 0 in reply to jelliott
    Intellectual 765 points
    Hi... i'm sorry to bother you... but i came up with another question...
    You said i could have my SCKI sourced by the McASP0's MCLK... my question is... which is the mcasp0's MCLK? I assume is one of the mcasp0_ahclkr/x... but as i have only one SCKI i don't know which one to use... if i use mcasp0_ahclkr for SCKI of the codec... then would my transmit operations from codec to the processor be synchronized also? i can use only mcasp_ahclkr and configure the mcasp0_ahclkx to the same frequency and both be synchronized this way... am i right?
    If i'm right, then i just have to connect mcasp_ahclkr to SCKI pin and i'm done... If not... i don't know what to do
  • 0 in reply to Pablo Fonovich
    Intellectual 765 points
    By the way... everything was thinking about the codec as slave...
  • 0 in reply to Pablo Fonovich
    Expert 1510 points

    If you are setting McASP as clock master, then it will generate BLCK and WCLK from MCLK.  The MCLK on Sitara EVMs is sourced by the 24 MHz crystal, so getting the clocks you need is a matter of dividing down from 24 MHz (Note that MCLK can also be divided).

    Please see this section of the Audio DAC Example to understand how to set these clocks in the ALSA driver.

  • 0 in reply to jelliott
    Intellectual 765 points

    Thanks for your answer... but either i'm not understanding your answer, or i'm not making my question properly....

    It's more a hardware issue...

    I have this pins on the beaglebone's mcasp0:

    -mcasp0_aclkr

    -mcasp0_aclkx

    -mcasp0_fsr

    -mcasp0_fsx

    -mcasp0_ahclkr

    -mcasp0_ahclkx

    And i have this pins on the codec:

    -BCLKAD

    -BCLKDA

    -LRCLKAD

    -LRCLKDA

    -SCKI

    Reading in datasheet to understand each pin... i came to this conections:

    mcasp0_aclkr -->BCLKAD

    mcasp0_aclkx -->BCLKDA

    mcasp0_fsr -->LRCLKAD

    mcasp0_fsx -->LRCLKDA

    ????????? -->SCKI

    So I have this options:

    1)Use mcasp0_ahclkr or mcasp0_ahclkx for SCKI (as far as i've read, i can use them for it)... but as i have to use the codec for both transmitting and recieving i don't know if a can use only one of them for SCKI mantaining both in same configuration...

    2)Use an externall clock for the three pins (SCKI, mcasp0_ahclkr and mcasp0_ahclkx) using the mcasp configuration as mixed (i've read of that in te TRM of AM355x)

    The question put in simple words would be: What pin of the mcasp should i use to source the SCKI of the codec?

    Can i use either mcasp0_ahclkr OR mcasp0_ahclkx?

  • 0 in reply to Pablo Fonovich
    TI__Genius 15900 points

    Hi Pablo,

    You might find Section 22.2.4 of the TRM helpful.  This section states:

    In operation, the transmitter uses ACLKX as the serial clock, and the receiver uses ACLKR as the serial clock. Optionally, the receiver can use ACLKX as the serial clock when the transmitter and receiver of the McASP are configured to operate synchronously.

    I assume you plan to have the receiver and transmitter operate synchronously.  If so, you can just connect SCKI to mcasp0_ahclkx.  Section 22.2.5.2 of the TRM describes how to configure the receiver to operate synchronously from ACLKX.

    Regards,

    Melissa

  • 0 in reply to melissaw
    Intellectual 765 points
    Hi:
    That was just what i was asking!
    I've read that part of the TRM, but i just wasnt' sure if the same applies to the ahclkx, as it only states for the bit clock acklx...
    But now i am thinking my other conections are wrong...
    I mean... if a use the mcasp0_ahclkx for SCKI, as that clock would be for both transmiter and reciever, i would have to connect both BCLKAD and BCLKDA to mcasp0_aclkx and both LRCLKDA and LRCLKAD to mcasp0_fsx... Am i right? so i just ignore the recieve clock signals, and use transmitter clock signals for everything? That's what i understand about configuring both syncrhonously in the TMR..

    And what about if i want the reciever and transmitter to opperate async??
    I think the solution should be using an unique external clock source for both ahclkx and ahclkr, and generating the rest of the signals by dividing them; and that same clock source connected to de SCKI? this way all ahclkx, ahclkr and SCKI would be synchronized, but i can configure the rest of the clock signals different for transmitter and reciever... am i right with this? Is there a more simple solution?

    If what i inted to do is to record and playback what is being recorded at "real time", would you recommend me sync over async?